Vandita Kulkarni 20eea462bf drm/i915/icl: Ungate ddi clocks before IO enable ... IO enable sequencing needs ddi clocks enabled. These clocks will be gated at a later point in the enable sequence. v2: Fix the commit header (Uma) v3: Remove the redundant read (Ville) Fixes: 949fc52af1 ("drm/i915/icl: add pll mapping for DSI") Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1553513202-13863-1-git-send-email-vandita.kulkarni@intel.com (cherry picked from commit c5b81a3252) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>		2019-04-10 09:06:29 -07:00
..
drm	drm/i915/icl: Ungate ddi clocks before IO enable	2019-04-10 09:06:29 -07:00
host1x	gpu: host1x: Continue CDMA execution starting with a next job	2019-02-07 18:34:25 +01:00
ipu-v3	media updates for v5.1-rc1	2019-03-09 14:45:54 -08:00
vga	- qxl: Remove the conflicting framebuffers earlier	2019-03-14 11:37:46 +10:00
Makefile