a3f048b542
Update PSCI DT bindings to allow to represent idle states for CPUs and the CPU topology, by using a hierarchical layout. Primarily this is done by re-using the existing DT bindings for PM domains [1] and for PM domain idle states [2]. Let's also add an example into the document for the PSCI DT bindings, to clearly show the new hierarchical based layout. The currently supported flattened layout, is already described in the ARM idle states bindings [3], so let's leave that as is. [1] Documentation/devicetree/bindings/power/power_domain.txt [2] Documentation/devicetree/bindings/power/domain-idle-state.txt [3] Documentation/devicetree/bindings/arm/idle-states.txt Co-developed-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
268 lines
7.7 KiB
YAML
268 lines
7.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/psci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Power State Coordination Interface (PSCI)
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maintainers:
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- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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description: |+
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Firmware implementing the PSCI functions described in ARM document number
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ARM DEN 0022A ("Power State Coordination Interface System Software on ARM
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processors") can be used by Linux to initiate various CPU-centric power
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operations.
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Issue A of the specification describes functions for CPU suspend, hotplug
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and migration of secure software.
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Functions are invoked by trapping to the privilege level of the PSCI
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firmware (specified as part of the binding below) and passing arguments
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in a manner similar to that specified by AAPCS:
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r0 => 32-bit Function ID / return value
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{r1 - r3} => Parameters
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Note that the immediate field of the trapping instruction must be set
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to #0.
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[2] Power State Coordination Interface (PSCI) specification
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http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
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properties:
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compatible:
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oneOf:
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- description:
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For implementations complying to PSCI versions prior to 0.2.
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const: arm,psci
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- description:
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For implementations complying to PSCI 0.2.
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const: arm,psci-0.2
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- description:
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For implementations complying to PSCI 0.2.
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Function IDs are not required and should be ignored by an OS with
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PSCI 0.2 support, but are permitted to be present for compatibility
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with existing software when "arm,psci" is later in the compatible
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list.
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items:
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- const: arm,psci-0.2
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- const: arm,psci
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- description:
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For implementations complying to PSCI 1.0.
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const: arm,psci-1.0
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- description:
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For implementations complying to PSCI 1.0.
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PSCI 1.0 is backward compatible with PSCI 0.2 with minor
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specification updates, as defined in the PSCI specification[2].
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items:
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- const: arm,psci-1.0
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- const: arm,psci-0.2
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method:
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description: The method of calling the PSCI firmware.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/string-array
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- enum:
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# SMC #0, with the register assignments specified in this binding.
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- smc
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# HVC #0, with the register assignments specified in this binding.
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- hvc
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cpu_suspend:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Function ID for CPU_SUSPEND operation
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cpu_off:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Function ID for CPU_OFF operation
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cpu_on:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Function ID for CPU_ON operation
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migrate:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Function ID for MIGRATE operation
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arm,psci-suspend-param:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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power_state parameter to pass to the PSCI suspend call.
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Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie
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idle state nodes with entry-method property is set to "psci", as per
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bindings in [1]) must specify this property.
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[1] Kernel documentation - ARM idle states bindings
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Documentation/devicetree/bindings/arm/idle-states.txt
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"#power-domain-cells":
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description:
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The number of cells in a PM domain specifier as per binding in [3].
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Must be 0 as to represent a single PM domain.
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ARM systems can have multiple cores, sometimes in an hierarchical
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arrangement. This often, but not always, maps directly to the processor
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power topology of the system. Individual nodes in a topology have their
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own specific power states and can be better represented hierarchically.
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For these cases, the definitions of the idle states for the CPUs and the
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CPU topology, must conform to the binding in [3]. The idle states
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themselves must conform to the binding in [4] and must specify the
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arm,psci-suspend-param property.
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It should also be noted that, in PSCI firmware v1.0 the OS-Initiated
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(OSI) CPU suspend mode is introduced. Using a hierarchical representation
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helps to implement support for OSI mode and OS implementations may choose
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to mandate it.
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[3] Documentation/devicetree/bindings/power/power_domain.txt
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[4] Documentation/devicetree/bindings/power/domain-idle-state.txt
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power-domains:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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description:
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List of phandles and PM domain specifiers, as defined by bindings of the
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PM domain provider.
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required:
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- compatible
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- method
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: arm,psci
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then:
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required:
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- cpu_off
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- cpu_on
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examples:
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- |+
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// Case 1: PSCI v0.1 only.
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_suspend = <0x95c10000>;
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cpu_off = <0x95c10001>;
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cpu_on = <0x95c10002>;
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migrate = <0x95c10003>;
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};
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- |+
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// Case 2: PSCI v0.2 only
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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- |+
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// Case 3: PSCI v0.2 and PSCI v0.1.
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/*
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* A DTB may provide IDs for use by kernels without PSCI 0.2 support,
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* enabling firmware and hypervisors to support existing and new kernels.
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* These IDs will be ignored by kernels with PSCI 0.2 support, which will
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* use the standard PSCI 0.2 IDs exclusively.
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*/
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psci {
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compatible = "arm,psci-0.2", "arm,psci";
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method = "hvc";
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cpu_on = <0x95c10002>;
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cpu_off = <0x95c10001>;
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};
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- |+
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// Case 4: CPUs and CPU idle states described using the hierarchical model.
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0>;
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enable-method = "psci";
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x100>;
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enable-method = "psci";
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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};
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idle-states {
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CPU_PWRDN: cpu-power-down {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0000001>;
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entry-latency-us = <10>;
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exit-latency-us = <10>;
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min-residency-us = <100>;
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};
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CLUSTER_RET: cluster-retention {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x1000011>;
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entry-latency-us = <500>;
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exit-latency-us = <500>;
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min-residency-us = <2000>;
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};
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CLUSTER_PWRDN: cluster-power-down {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x1000031>;
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entry-latency-us = <2000>;
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exit-latency-us = <2000>;
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min-residency-us = <6000>;
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: cpu-pd0 {
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#power-domain-cells = <0>;
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domain-idle-states = <&CPU_PWRDN>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD1: cpu-pd1 {
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#power-domain-cells = <0>;
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domain-idle-states = <&CPU_PWRDN>;
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power-domains = <&CLUSTER_PD>;
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};
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CLUSTER_PD: cluster-pd {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
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};
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};
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...
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