forked from Minki/linux
207e21a973
All boards use clock event ratings of 200 for the MTU2, hardcode it in the driver. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Wolfram Sang <wsa@sang-engineering.com>
525 lines
12 KiB
C
525 lines
12 KiB
C
/*
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* SuperH Timer Support - MTU2
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*
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/clockchips.h>
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#include <linux/sh_timer.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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struct sh_mtu2_device;
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struct sh_mtu2_channel {
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struct sh_mtu2_device *mtu;
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unsigned int index;
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void __iomem *base;
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int irq;
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struct clock_event_device ced;
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};
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struct sh_mtu2_device {
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struct platform_device *pdev;
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void __iomem *mapbase;
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struct clk *clk;
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struct sh_mtu2_channel *channels;
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unsigned int num_channels;
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};
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static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
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#define TSTR -1 /* shared register */
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#define TCR 0 /* channel register */
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#define TMDR 1 /* channel register */
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#define TIOR 2 /* channel register */
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#define TIER 3 /* channel register */
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#define TSR 4 /* channel register */
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#define TCNT 5 /* channel register */
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#define TGR 6 /* channel register */
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#define TCR_CCLR_NONE (0 << 5)
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#define TCR_CCLR_TGRA (1 << 5)
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#define TCR_CCLR_TGRB (2 << 5)
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#define TCR_CCLR_SYNC (3 << 5)
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#define TCR_CCLR_TGRC (5 << 5)
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#define TCR_CCLR_TGRD (6 << 5)
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#define TCR_CCLR_MASK (7 << 5)
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#define TCR_CKEG_RISING (0 << 3)
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#define TCR_CKEG_FALLING (1 << 3)
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#define TCR_CKEG_BOTH (2 << 3)
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#define TCR_CKEG_MASK (3 << 3)
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/* Values 4 to 7 are channel-dependent */
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#define TCR_TPSC_P1 (0 << 0)
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#define TCR_TPSC_P4 (1 << 0)
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#define TCR_TPSC_P16 (2 << 0)
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#define TCR_TPSC_P64 (3 << 0)
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#define TCR_TPSC_CH0_TCLKA (4 << 0)
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#define TCR_TPSC_CH0_TCLKB (5 << 0)
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#define TCR_TPSC_CH0_TCLKC (6 << 0)
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#define TCR_TPSC_CH0_TCLKD (7 << 0)
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#define TCR_TPSC_CH1_TCLKA (4 << 0)
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#define TCR_TPSC_CH1_TCLKB (5 << 0)
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#define TCR_TPSC_CH1_P256 (6 << 0)
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#define TCR_TPSC_CH1_TCNT2 (7 << 0)
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#define TCR_TPSC_CH2_TCLKA (4 << 0)
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#define TCR_TPSC_CH2_TCLKB (5 << 0)
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#define TCR_TPSC_CH2_TCLKC (6 << 0)
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#define TCR_TPSC_CH2_P1024 (7 << 0)
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#define TCR_TPSC_CH34_P256 (4 << 0)
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#define TCR_TPSC_CH34_P1024 (5 << 0)
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#define TCR_TPSC_CH34_TCLKA (6 << 0)
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#define TCR_TPSC_CH34_TCLKB (7 << 0)
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#define TCR_TPSC_MASK (7 << 0)
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#define TMDR_BFE (1 << 6)
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#define TMDR_BFB (1 << 5)
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#define TMDR_BFA (1 << 4)
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#define TMDR_MD_NORMAL (0 << 0)
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#define TMDR_MD_PWM_1 (2 << 0)
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#define TMDR_MD_PWM_2 (3 << 0)
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#define TMDR_MD_PHASE_1 (4 << 0)
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#define TMDR_MD_PHASE_2 (5 << 0)
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#define TMDR_MD_PHASE_3 (6 << 0)
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#define TMDR_MD_PHASE_4 (7 << 0)
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#define TMDR_MD_PWM_SYNC (8 << 0)
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#define TMDR_MD_PWM_COMP_CREST (13 << 0)
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#define TMDR_MD_PWM_COMP_TROUGH (14 << 0)
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#define TMDR_MD_PWM_COMP_BOTH (15 << 0)
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#define TMDR_MD_MASK (15 << 0)
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#define TIOC_IOCH(n) ((n) << 4)
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#define TIOC_IOCL(n) ((n) << 0)
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#define TIOR_OC_RETAIN (0 << 0)
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#define TIOR_OC_0_CLEAR (1 << 0)
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#define TIOR_OC_0_SET (2 << 0)
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#define TIOR_OC_0_TOGGLE (3 << 0)
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#define TIOR_OC_1_CLEAR (5 << 0)
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#define TIOR_OC_1_SET (6 << 0)
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#define TIOR_OC_1_TOGGLE (7 << 0)
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#define TIOR_IC_RISING (8 << 0)
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#define TIOR_IC_FALLING (9 << 0)
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#define TIOR_IC_BOTH (10 << 0)
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#define TIOR_IC_TCNT (12 << 0)
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#define TIOR_MASK (15 << 0)
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#define TIER_TTGE (1 << 7)
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#define TIER_TTGE2 (1 << 6)
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#define TIER_TCIEU (1 << 5)
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#define TIER_TCIEV (1 << 4)
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#define TIER_TGIED (1 << 3)
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#define TIER_TGIEC (1 << 2)
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#define TIER_TGIEB (1 << 1)
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#define TIER_TGIEA (1 << 0)
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#define TSR_TCFD (1 << 7)
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#define TSR_TCFU (1 << 5)
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#define TSR_TCFV (1 << 4)
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#define TSR_TGFD (1 << 3)
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#define TSR_TGFC (1 << 2)
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#define TSR_TGFB (1 << 1)
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#define TSR_TGFA (1 << 0)
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static unsigned long mtu2_reg_offs[] = {
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[TCR] = 0,
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[TMDR] = 1,
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[TIOR] = 2,
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[TIER] = 4,
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[TSR] = 5,
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[TCNT] = 6,
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[TGR] = 8,
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};
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static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
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{
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unsigned long offs;
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if (reg_nr == TSTR)
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return ioread8(ch->mtu->mapbase);
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offs = mtu2_reg_offs[reg_nr];
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if ((reg_nr == TCNT) || (reg_nr == TGR))
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return ioread16(ch->base + offs);
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else
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return ioread8(ch->base + offs);
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}
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static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
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unsigned long value)
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{
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unsigned long offs;
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if (reg_nr == TSTR) {
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iowrite8(value, ch->mtu->mapbase);
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return;
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}
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offs = mtu2_reg_offs[reg_nr];
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if ((reg_nr == TCNT) || (reg_nr == TGR))
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iowrite16(value, ch->base + offs);
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else
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iowrite8(value, ch->base + offs);
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}
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static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
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{
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
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value = sh_mtu2_read(ch, TSTR);
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if (start)
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value |= 1 << ch->index;
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else
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value &= ~(1 << ch->index);
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sh_mtu2_write(ch, TSTR, value);
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raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
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}
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static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
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{
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unsigned long periodic;
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unsigned long rate;
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int ret;
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pm_runtime_get_sync(&ch->mtu->pdev->dev);
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dev_pm_syscore_device(&ch->mtu->pdev->dev, true);
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/* enable clock */
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ret = clk_enable(ch->mtu->clk);
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if (ret) {
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dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
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ch->index);
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return ret;
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}
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/* make sure channel is disabled */
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sh_mtu2_start_stop_ch(ch, 0);
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rate = clk_get_rate(ch->mtu->clk) / 64;
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periodic = (rate + HZ/2) / HZ;
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/*
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* "Periodic Counter Operation"
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* Clear on TGRA compare match, divide clock by 64.
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*/
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sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
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sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |
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TIOC_IOCL(TIOR_OC_0_CLEAR));
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sh_mtu2_write(ch, TGR, periodic);
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sh_mtu2_write(ch, TCNT, 0);
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sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);
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sh_mtu2_write(ch, TIER, TIER_TGIEA);
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/* enable channel */
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sh_mtu2_start_stop_ch(ch, 1);
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return 0;
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}
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static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
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{
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/* disable channel */
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sh_mtu2_start_stop_ch(ch, 0);
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/* stop clock */
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clk_disable(ch->mtu->clk);
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dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
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pm_runtime_put(&ch->mtu->pdev->dev);
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}
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static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
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{
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struct sh_mtu2_channel *ch = dev_id;
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/* acknowledge interrupt */
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sh_mtu2_read(ch, TSR);
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sh_mtu2_write(ch, TSR, ~TSR_TGFA);
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/* notify clockevent layer */
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ch->ced.event_handler(&ch->ced);
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return IRQ_HANDLED;
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}
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static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
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{
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return container_of(ced, struct sh_mtu2_channel, ced);
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}
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static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
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struct clock_event_device *ced)
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{
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struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
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int disabled = 0;
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/* deal with old setting first */
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switch (ced->mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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sh_mtu2_disable(ch);
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disabled = 1;
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break;
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default:
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break;
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}
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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dev_info(&ch->mtu->pdev->dev,
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"ch%u: used for periodic clock events\n", ch->index);
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sh_mtu2_enable(ch);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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if (!disabled)
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sh_mtu2_disable(ch);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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break;
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}
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}
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static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
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}
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static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
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}
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static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
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const char *name)
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{
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struct clock_event_device *ced = &ch->ced;
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int ret;
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ced->name = name;
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ced->features = CLOCK_EVT_FEAT_PERIODIC;
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ced->rating = 200;
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ced->cpumask = cpu_possible_mask;
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ced->set_mode = sh_mtu2_clock_event_mode;
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ced->suspend = sh_mtu2_clock_event_suspend;
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ced->resume = sh_mtu2_clock_event_resume;
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dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
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ch->index);
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clockevents_register_device(ced);
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ret = request_irq(ch->irq, sh_mtu2_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
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dev_name(&ch->mtu->pdev->dev), ch);
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if (ret) {
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dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
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ch->index, ch->irq);
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return;
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}
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}
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static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name,
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bool clockevent)
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{
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if (clockevent)
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sh_mtu2_register_clockevent(ch, name);
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return 0;
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}
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static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch,
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struct sh_mtu2_device *mtu)
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{
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struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
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ch->mtu = mtu;
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ch->index = cfg->timer_bit;
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ch->irq = platform_get_irq(mtu->pdev, 0);
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if (ch->irq < 0) {
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dev_err(&mtu->pdev->dev, "ch%u: failed to get irq\n",
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ch->index);
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return ch->irq;
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}
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return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev),
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cfg->clockevent_rating != 0);
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}
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static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
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struct platform_device *pdev)
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{
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struct sh_timer_config *cfg = pdev->dev.platform_data;
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struct resource *res;
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void __iomem *base;
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int ret;
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ret = -ENXIO;
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mtu->pdev = pdev;
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if (!cfg) {
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dev_err(&mtu->pdev->dev, "missing platform data\n");
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goto err0;
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}
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platform_set_drvdata(pdev, mtu);
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res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&mtu->pdev->dev, "failed to get I/O memory\n");
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goto err0;
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}
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/*
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* Map memory, let base point to our channel and mapbase to the
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* start/stop shared register.
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*/
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base = ioremap_nocache(res->start, resource_size(res));
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if (base == NULL) {
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dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n");
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goto err0;
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}
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mtu->mapbase = base + cfg->channel_offset;
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/* get hold of clock */
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mtu->clk = clk_get(&mtu->pdev->dev, "mtu2_fck");
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if (IS_ERR(mtu->clk)) {
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dev_err(&mtu->pdev->dev, "cannot get clock\n");
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ret = PTR_ERR(mtu->clk);
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goto err1;
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}
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ret = clk_prepare(mtu->clk);
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if (ret < 0)
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goto err2;
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mtu->channels = kzalloc(sizeof(*mtu->channels), GFP_KERNEL);
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if (mtu->channels == NULL) {
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ret = -ENOMEM;
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goto err3;
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}
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mtu->num_channels = 1;
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mtu->channels[0].base = base;
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ret = sh_mtu2_setup_channel(&mtu->channels[0], mtu);
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if (ret < 0)
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goto err3;
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return 0;
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err3:
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kfree(mtu->channels);
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clk_unprepare(mtu->clk);
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err2:
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clk_put(mtu->clk);
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err1:
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iounmap(base);
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err0:
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return ret;
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}
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static int sh_mtu2_probe(struct platform_device *pdev)
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{
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struct sh_mtu2_device *mtu = platform_get_drvdata(pdev);
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struct sh_timer_config *cfg = pdev->dev.platform_data;
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int ret;
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if (!is_early_platform_device(pdev)) {
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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}
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if (mtu) {
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dev_info(&pdev->dev, "kept as earlytimer\n");
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goto out;
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}
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mtu = kzalloc(sizeof(*mtu), GFP_KERNEL);
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if (mtu == NULL) {
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dev_err(&pdev->dev, "failed to allocate driver data\n");
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return -ENOMEM;
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}
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ret = sh_mtu2_setup(mtu, pdev);
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if (ret) {
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kfree(mtu);
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pm_runtime_idle(&pdev->dev);
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return ret;
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}
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if (is_early_platform_device(pdev))
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return 0;
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out:
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if (cfg->clockevent_rating)
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pm_runtime_irq_safe(&pdev->dev);
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|
else
|
|
pm_runtime_idle(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_mtu2_remove(struct platform_device *pdev)
|
|
{
|
|
return -EBUSY; /* cannot unregister clockevent */
|
|
}
|
|
|
|
static struct platform_driver sh_mtu2_device_driver = {
|
|
.probe = sh_mtu2_probe,
|
|
.remove = sh_mtu2_remove,
|
|
.driver = {
|
|
.name = "sh_mtu2",
|
|
}
|
|
};
|
|
|
|
static int __init sh_mtu2_init(void)
|
|
{
|
|
return platform_driver_register(&sh_mtu2_device_driver);
|
|
}
|
|
|
|
static void __exit sh_mtu2_exit(void)
|
|
{
|
|
platform_driver_unregister(&sh_mtu2_device_driver);
|
|
}
|
|
|
|
early_platform_init("earlytimer", &sh_mtu2_device_driver);
|
|
subsys_initcall(sh_mtu2_init);
|
|
module_exit(sh_mtu2_exit);
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
|
|
MODULE_LICENSE("GPL v2");
|