38bc036130
The current msi_ops are short sighted in a number of ways, this patch attempts to fix the glaring deficiences. - Report in msi_ops if a 64bit address is needed in the msi message, so we can fail 32bit only msi structures. - Send and receive a full struct msi_msg in both setup and target. This is a little cleaner and allows for architectures that need to modify the data to retarget the msi interrupt to a different cpu. - In target pass in the full cpu mask instead of just the first cpu in case we can make use of the full cpu mask. - Operate in terms of irqs and not vectors, currently there is still a 1-1 relationship but on architectures other than ia64 I expect this will change. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rajesh Shah <rajesh.shah@intel.com> Cc: Andi Kleen <ak@muc.de> Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/*
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* MSI hooks for standard x86 apic
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*/
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/smp.h>
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#include "msi.h"
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/*
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* Shifts for APIC-based data
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*/
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#define MSI_DATA_VECTOR_SHIFT 0
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#define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT)
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#define MSI_DATA_DELIVERY_SHIFT 8
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#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_SHIFT)
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#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_SHIFT)
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#define MSI_DATA_LEVEL_SHIFT 14
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#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
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#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
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#define MSI_DATA_TRIGGER_SHIFT 15
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#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
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#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
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/*
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* Shift/mask fields for APIC-based bus address
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*/
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#define MSI_ADDR_HEADER 0xfee00000
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#define MSI_ADDR_DESTID_MASK 0xfff0000f
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#define MSI_ADDR_DESTID_CPU(cpu) ((cpu) << MSI_TARGET_CPU_SHIFT)
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#define MSI_ADDR_DESTMODE_SHIFT 2
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#define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT)
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#define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT)
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#define MSI_ADDR_REDIRECTION_SHIFT 3
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#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
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#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
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static void
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msi_target_apic(unsigned int irq, cpumask_t cpu_mask, struct msi_msg *msg)
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{
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u32 addr = msg->address_lo;
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addr &= MSI_ADDR_DESTID_MASK;
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addr |= MSI_ADDR_DESTID_CPU(cpu_physical_id(first_cpu(cpu_mask)));
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msg->address_lo = addr;
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}
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static int
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msi_setup_apic(struct pci_dev *pdev, /* unused in generic */
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unsigned int irq,
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struct msi_msg *msg)
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{
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unsigned long dest_phys_id;
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unsigned int vector;
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dest_phys_id = cpu_physical_id(first_cpu(cpu_online_map));
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vector = irq;
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msg->address_hi = 0;
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msg->address_lo =
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MSI_ADDR_HEADER |
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MSI_ADDR_DESTMODE_PHYS |
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MSI_ADDR_REDIRECTION_CPU |
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MSI_ADDR_DESTID_CPU(dest_phys_id);
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msg->data =
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MSI_DATA_TRIGGER_EDGE |
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MSI_DATA_LEVEL_ASSERT |
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MSI_DATA_DELIVERY_FIXED |
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MSI_DATA_VECTOR(vector);
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return 0;
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}
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static void
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msi_teardown_apic(unsigned int irq)
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{
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return; /* no-op */
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}
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/*
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* Generic ops used on most IA archs/platforms. Set with msi_register()
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*/
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struct msi_ops msi_apic_ops = {
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.needs_64bit_address = 0,
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.setup = msi_setup_apic,
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.teardown = msi_teardown_apic,
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.target = msi_target_apic,
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};
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