forked from Minki/linux
1f75ff0a3d
We want to use the virtual counter at EL0, as the physical counter may not track the current clocksource for guests running under a hypervisor. This patch updates the vdso and generic timer driver to use the virtual counter. The kernel EL2 entry code is also updated to ensure that the virtual offset is initialised to zero. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
512 lines
13 KiB
ArmAsm
512 lines
13 KiB
ArmAsm
/*
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* Low-level CPU initialisation
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* Based on arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (C) 2003-2012 ARM Ltd.
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* Authors: Catalin Marinas <catalin.marinas@arm.com>
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* Will Deacon <will.deacon@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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/*
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* swapper_pg_dir is the virtual address of the initial page table. We place
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* the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
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* 2 pages and is placed below swapper_pg_dir.
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*/
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#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
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#if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
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#error KERNEL_RAM_VADDR must start at 0xXXX80000
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#endif
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#define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
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#define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
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.globl swapper_pg_dir
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.equ swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
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.globl idmap_pg_dir
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.equ idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
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.macro pgtbl, ttb0, ttb1, phys
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add \ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
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sub \ttb0, \ttb1, #IDMAP_DIR_SIZE
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.endm
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#ifdef CONFIG_ARM64_64K_PAGES
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#define BLOCK_SHIFT PAGE_SHIFT
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#define BLOCK_SIZE PAGE_SIZE
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#else
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#define BLOCK_SHIFT SECTION_SHIFT
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#define BLOCK_SIZE SECTION_SIZE
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#endif
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#define KERNEL_START KERNEL_RAM_VADDR
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#define KERNEL_END _end
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/*
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* Initial memory map attributes.
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*/
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#ifndef CONFIG_SMP
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#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
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#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
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#else
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#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
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#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
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#endif
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#ifdef CONFIG_ARM64_64K_PAGES
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#define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
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#define IO_MMUFLAGS PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_XN | PTE_FLAGS
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#else
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#define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
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#define IO_MMUFLAGS PMD_ATTRINDX(MT_DEVICE_nGnRE) | PMD_SECT_XN | PMD_FLAGS
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#endif
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* The requirements are:
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* MMU = off, D-cache = off, I-cache = on or off,
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* x0 = physical address to the FDT blob.
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*
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* This code is mostly position independent so you call this at
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* __pa(PAGE_OFFSET + TEXT_OFFSET).
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*
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* Note that the callee-saved registers are used for storing variables
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* that are useful before the MMU is enabled. The allocations are described
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* in the entry routines.
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*/
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__HEAD
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/*
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* DO NOT MODIFY. Image header expected by Linux boot-loaders.
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*/
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b stext // branch to kernel start, magic
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.long 0 // reserved
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.quad TEXT_OFFSET // Image load offset from start of RAM
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.quad 0 // reserved
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.quad 0 // reserved
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ENTRY(stext)
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mov x21, x0 // x21=FDT
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bl el2_setup // Drop to EL1
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mrs x22, midr_el1 // x22=cpuid
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mov x0, x22
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bl lookup_processor_type
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mov x23, x0 // x23=current cpu_table
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cbz x23, __error_p // invalid processor (x23=0)?
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bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
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bl __vet_fdt
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bl __create_page_tables // x25=TTBR0, x26=TTBR1
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/*
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* The following calls CPU specific code in a position independent
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* manner. See arch/arm64/mm/proc.S for details. x23 = base of
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* cpu_info structure selected by lookup_processor_type above.
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* On return, the CPU will be ready for the MMU to be turned on and
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* the TCR will have been set.
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*/
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ldr x27, __switch_data // address to jump to after
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// MMU has been enabled
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adr lr, __enable_mmu // return (PIC) address
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ldr x12, [x23, #CPU_INFO_SETUP]
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add x12, x12, x28 // __virt_to_phys
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br x12 // initialise processor
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ENDPROC(stext)
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/*
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* If we're fortunate enough to boot at EL2, ensure that the world is
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* sane before dropping to EL1.
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*/
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ENTRY(el2_setup)
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mrs x0, CurrentEL
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cmp x0, #PSR_MODE_EL2t
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ccmp x0, #PSR_MODE_EL2h, #0x4, ne
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b.eq 1f
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ret
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/* Hyp configuration. */
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1: mov x0, #(1 << 31) // 64-bit EL1
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msr hcr_el2, x0
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/* Generic timers. */
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mrs x0, cnthctl_el2
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orr x0, x0, #3 // Enable EL1 physical timers
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msr cnthctl_el2, x0
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msr cntvoff_el2, xzr // Clear virtual offset
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/* Populate ID registers. */
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mrs x0, midr_el1
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mrs x1, mpidr_el1
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msr vpidr_el2, x0
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msr vmpidr_el2, x1
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/* sctlr_el1 */
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mov x0, #0x0800 // Set/clear RES{1,0} bits
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movk x0, #0x30d0, lsl #16
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msr sctlr_el1, x0
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/* Coprocessor traps. */
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mov x0, #0x33ff
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msr cptr_el2, x0 // Disable copro. traps to EL2
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#ifdef CONFIG_COMPAT
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msr hstr_el2, xzr // Disable CP15 traps to EL2
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#endif
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/* spsr */
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mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
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PSR_MODE_EL1h)
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msr spsr_el2, x0
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msr elr_el2, lr
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eret
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ENDPROC(el2_setup)
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.align 3
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2: .quad .
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.quad PAGE_OFFSET
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#ifdef CONFIG_SMP
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.pushsection .smp.pen.text, "ax"
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.align 3
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1: .quad .
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.quad secondary_holding_pen_release
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/*
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* This provides a "holding pen" for platforms to hold all secondary
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* cores are held until we're ready for them to initialise.
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*/
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ENTRY(secondary_holding_pen)
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bl el2_setup // Drop to EL1
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mrs x0, mpidr_el1
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and x0, x0, #15 // CPU number
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adr x1, 1b
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ldp x2, x3, [x1]
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sub x1, x1, x2
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add x3, x3, x1
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pen: ldr x4, [x3]
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cmp x4, x0
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b.eq secondary_startup
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wfe
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b pen
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ENDPROC(secondary_holding_pen)
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.popsection
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ENTRY(secondary_startup)
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/*
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* Common entry point for secondary CPUs.
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*/
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mrs x22, midr_el1 // x22=cpuid
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mov x0, x22
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bl lookup_processor_type
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mov x23, x0 // x23=current cpu_table
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cbz x23, __error_p // invalid processor (x23=0)?
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bl __calc_phys_offset // x24=phys offset
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pgtbl x25, x26, x24 // x25=TTBR0, x26=TTBR1
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ldr x12, [x23, #CPU_INFO_SETUP]
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add x12, x12, x28 // __virt_to_phys
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blr x12 // initialise processor
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ldr x21, =secondary_data
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ldr x27, =__secondary_switched // address to jump to after enabling the MMU
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b __enable_mmu
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ENDPROC(secondary_startup)
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ENTRY(__secondary_switched)
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ldr x0, [x21] // get secondary_data.stack
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mov sp, x0
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mov x29, #0
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b secondary_start_kernel
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ENDPROC(__secondary_switched)
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#endif /* CONFIG_SMP */
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/*
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* Setup common bits before finally enabling the MMU. Essentially this is just
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* loading the page table pointer and vector base registers.
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*
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* On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
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* the MMU.
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*/
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__enable_mmu:
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ldr x5, =vectors
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msr vbar_el1, x5
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msr ttbr0_el1, x25 // load TTBR0
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msr ttbr1_el1, x26 // load TTBR1
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isb
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b __turn_mmu_on
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ENDPROC(__enable_mmu)
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/*
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* Enable the MMU. This completely changes the structure of the visible memory
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* space. You will not be able to trace execution through this.
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*
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* x0 = system control register
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* x27 = *virtual* address to jump to upon completion
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*
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* other registers depend on the function called upon completion
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*/
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.align 6
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__turn_mmu_on:
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msr sctlr_el1, x0
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isb
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br x27
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ENDPROC(__turn_mmu_on)
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/*
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* Calculate the start of physical memory.
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*/
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__calc_phys_offset:
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adr x0, 1f
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ldp x1, x2, [x0]
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sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
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add x24, x2, x28 // x24 = PHYS_OFFSET
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ret
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ENDPROC(__calc_phys_offset)
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.align 3
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1: .quad .
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.quad PAGE_OFFSET
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/*
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* Macro to populate the PGD for the corresponding block entry in the next
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* level (tbl) for the given virtual address.
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*
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* Preserves: pgd, tbl, virt
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* Corrupts: tmp1, tmp2
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*/
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.macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
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lsr \tmp1, \virt, #PGDIR_SHIFT
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and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
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orr \tmp2, \tbl, #3 // PGD entry table type
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str \tmp2, [\pgd, \tmp1, lsl #3]
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.endm
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/*
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* Macro to populate block entries in the page table for the start..end
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* virtual range (inclusive).
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*
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* Preserves: tbl, flags
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* Corrupts: phys, start, end, pstate
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*/
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.macro create_block_map, tbl, flags, phys, start, end, idmap=0
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lsr \phys, \phys, #BLOCK_SHIFT
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.if \idmap
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and \start, \phys, #PTRS_PER_PTE - 1 // table index
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.else
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lsr \start, \start, #BLOCK_SHIFT
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and \start, \start, #PTRS_PER_PTE - 1 // table index
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.endif
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orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
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.ifnc \start,\end
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lsr \end, \end, #BLOCK_SHIFT
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and \end, \end, #PTRS_PER_PTE - 1 // table end index
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.endif
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9999: str \phys, [\tbl, \start, lsl #3] // store the entry
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.ifnc \start,\end
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add \start, \start, #1 // next entry
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add \phys, \phys, #BLOCK_SIZE // next block
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cmp \start, \end
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b.ls 9999b
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.endif
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.endm
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/*
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* Setup the initial page tables. We only setup the barest amount which is
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* required to get the kernel running. The following sections are required:
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* - identity mapping to enable the MMU (low address, TTBR0)
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* - first few MB of the kernel linear mapping to jump to once the MMU has
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* been enabled, including the FDT blob (TTBR1)
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*/
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__create_page_tables:
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pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses
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/*
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* Clear the idmap and swapper page tables.
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*/
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mov x0, x25
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add x6, x26, #SWAPPER_DIR_SIZE
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1: stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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stp xzr, xzr, [x0], #16
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cmp x0, x6
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b.lo 1b
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ldr x7, =MM_MMUFLAGS
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/*
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* Create the identity mapping.
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*/
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add x0, x25, #PAGE_SIZE // section table address
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adr x3, __turn_mmu_on // virtual/physical address
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create_pgd_entry x25, x0, x3, x5, x6
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create_block_map x0, x7, x3, x5, x5, idmap=1
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/*
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* Map the kernel image (starting with PHYS_OFFSET).
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*/
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add x0, x26, #PAGE_SIZE // section table address
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mov x5, #PAGE_OFFSET
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create_pgd_entry x26, x0, x5, x3, x6
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ldr x6, =KERNEL_END - 1
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mov x3, x24 // phys offset
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create_block_map x0, x7, x3, x5, x6
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/*
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* Map the FDT blob (maximum 2MB; must be within 512MB of
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* PHYS_OFFSET).
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*/
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mov x3, x21 // FDT phys address
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and x3, x3, #~((1 << 21) - 1) // 2MB aligned
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mov x6, #PAGE_OFFSET
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sub x5, x3, x24 // subtract PHYS_OFFSET
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tst x5, #~((1 << 29) - 1) // within 512MB?
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csel x21, xzr, x21, ne // zero the FDT pointer
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b.ne 1f
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add x5, x5, x6 // __va(FDT blob)
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add x6, x5, #1 << 21 // 2MB for the FDT blob
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sub x6, x6, #1 // inclusive range
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create_block_map x0, x7, x3, x5, x6
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1:
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ret
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ENDPROC(__create_page_tables)
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.ltorg
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.align 3
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.type __switch_data, %object
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__switch_data:
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.quad __mmap_switched
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.quad __data_loc // x4
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.quad _data // x5
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.quad __bss_start // x6
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.quad _end // x7
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.quad processor_id // x4
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.quad __fdt_pointer // x5
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.quad memstart_addr // x6
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.quad init_thread_union + THREAD_START_SP // sp
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/*
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* The following fragment of code is executed with the MMU on in MMU mode, and
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* uses absolute addresses; this is not position independent.
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*/
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__mmap_switched:
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adr x3, __switch_data + 8
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ldp x4, x5, [x3], #16
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ldp x6, x7, [x3], #16
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cmp x4, x5 // Copy data segment if needed
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1: ccmp x5, x6, #4, ne
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b.eq 2f
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ldr x16, [x4], #8
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str x16, [x5], #8
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b 1b
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2:
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1: cmp x6, x7
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b.hs 2f
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str xzr, [x6], #8 // Clear BSS
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b 1b
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2:
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ldp x4, x5, [x3], #16
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ldr x6, [x3], #8
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ldr x16, [x3]
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mov sp, x16
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str x22, [x4] // Save processor ID
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str x21, [x5] // Save FDT pointer
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str x24, [x6] // Save PHYS_OFFSET
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mov x29, #0
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b start_kernel
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ENDPROC(__mmap_switched)
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/*
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* Exception handling. Something went wrong and we can't proceed. We ought to
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* tell the user, but since we don't have any guarantee that we're even
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* running on the right architecture, we do virtually nothing.
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*/
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__error_p:
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ENDPROC(__error_p)
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__error:
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1: nop
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b 1b
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ENDPROC(__error)
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/*
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* This function gets the processor ID in w0 and searches the cpu_table[] for
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* a match. It returns a pointer to the struct cpu_info it found. The
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* cpu_table[] must end with an empty (all zeros) structure.
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*
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* This routine can be called via C code and it needs to work with the MMU
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* both disabled and enabled (the offset is calculated automatically).
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*/
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ENTRY(lookup_processor_type)
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adr x1, __lookup_processor_type_data
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ldp x2, x3, [x1]
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sub x1, x1, x2 // get offset between VA and PA
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add x3, x3, x1 // convert VA to PA
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1:
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ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
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cbz w5, 2f // end of list?
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and w6, w6, w0
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cmp w5, w6
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b.eq 3f
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add x3, x3, #CPU_INFO_SZ
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b 1b
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2:
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mov x3, #0 // unknown processor
|
|
3:
|
|
mov x0, x3
|
|
ret
|
|
ENDPROC(lookup_processor_type)
|
|
|
|
.align 3
|
|
.type __lookup_processor_type_data, %object
|
|
__lookup_processor_type_data:
|
|
.quad .
|
|
.quad cpu_table
|
|
.size __lookup_processor_type_data, . - __lookup_processor_type_data
|
|
|
|
/*
|
|
* Determine validity of the x21 FDT pointer.
|
|
* The dtb must be 8-byte aligned and live in the first 512M of memory.
|
|
*/
|
|
__vet_fdt:
|
|
tst x21, #0x7
|
|
b.ne 1f
|
|
cmp x21, x24
|
|
b.lt 1f
|
|
mov x0, #(1 << 29)
|
|
add x0, x0, x24
|
|
cmp x21, x0
|
|
b.ge 1f
|
|
ret
|
|
1:
|
|
mov x21, #0
|
|
ret
|
|
ENDPROC(__vet_fdt)
|