6b5e741e9a
Implement the mips_cdmm_phys_base() platform callback to provide a default Common Device Memory Map (CDMM) physical base address for the Pistachio SoC. This allows the CDMM in each VPE to be configured and probed for devices, such as the Fast Debug Channel (FDC). The physical address chosen is just below the default CPC address, which appears to also be unallocated. The FDC IRQ is also usable on Pistachio, and is routed through the GIC, so implement the get_c0_fdc_int() platform callback using gic_get_c0_fdc_int(), so the FDC driver doesn't have to fall back to polling. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Cc: linux-mips@linux-mips.org Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Patchwork: http://patchwork.linux-mips.org/patch/9749/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
58 lines
1.1 KiB
C
58 lines
1.1 KiB
C
/*
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* Pistachio clocksource/timer setup
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*
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* Copyright (C) 2014 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/irqchip/mips-gic.h>
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#include <linux/of.h>
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#include <asm/time.h>
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unsigned int get_c0_compare_int(void)
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{
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return gic_get_c0_compare_int();
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}
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int get_c0_perfcount_int(void)
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{
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return gic_get_c0_perfcount_int();
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}
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int get_c0_fdc_int(void)
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{
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return gic_get_c0_fdc_int();
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}
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void __init plat_time_init(void)
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{
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struct device_node *np;
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struct clk *clk;
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of_clk_init(NULL);
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clocksource_of_init();
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np = of_get_cpu_node(0, NULL);
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if (!np) {
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pr_err("Failed to get CPU node\n");
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return;
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}
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
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return;
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}
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mips_hpt_frequency = clk_get_rate(clk) / 2;
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clk_put(clk);
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}
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