forked from Minki/linux
1e66235330
This moves the static, device-tied pin control configuration out of the board file board-mop500-pins.c and into the device tree. Add entries for SDI1 and SDI2 on the Snowball so that the WLAN pins on SDI1 can be used further on, and the unused pins on SDI2 can be put to sleep. Cc: Lee Jones <lee.jones@linaro.org> Cc: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
431 lines
9.8 KiB
Plaintext
431 lines
9.8 KiB
Plaintext
/*
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* Copyright 2013 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "ste-nomadik-pinctrl.dtsi"
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/ {
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soc {
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pinctrl {
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/* Settings for all UART default and sleep states */
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uart0 {
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uart0_default_mode: uart0_default {
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default_mux {
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ste,function = "u0";
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ste,pins = "u0_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
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ste,config = <&out_hi>;
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};
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};
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uart0_sleep_mode: uart0_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO1_AJ3"; /* RTS */
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ste,config = <&slpm_out_hi_wkup_pdis>;
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};
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sleep_cfg3 {
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ste,pins = "GPIO3_AH3"; /* TXD */
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ste,config = <&slpm_out_wkup_pdis>;
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};
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};
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};
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uart1 {
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uart1_default_mode: uart1_default {
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default_mux {
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ste,function = "u1";
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ste,pins = "u1rxtx_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO4_AH6"; /* RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO5_AG6"; /* TXD */
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ste,config = <&out_hi>;
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};
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};
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uart1_sleep_mode: uart1_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO4_AH6"; /* RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO5_AG6"; /* TXD */
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ste,config = <&slpm_out_wkup_pdis>;
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};
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};
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};
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uart2 {
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uart2_default_mode: uart2_default {
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default_mux {
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ste,function = "u2";
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ste,pins = "u2rxtx_c_1";
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};
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default_cfg1 {
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ste,pins = "GPIO29_W2"; /* RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO30_W3"; /* TXD */
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ste,config = <&out_hi>;
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};
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};
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uart2_sleep_mode: uart2_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO29_W2"; /* RXD */
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ste,config = <&in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO30_W3"; /* TXD */
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ste,config = <&out_wkup_pdis>;
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};
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};
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};
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/* Settings for all I2C default and sleep states */
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i2c0 {
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i2c0_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c0";
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ste,pins = "i2c0_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c0_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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i2c1 {
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i2c1_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c1";
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ste,pins = "i2c1_b_2";
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};
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default_cfg1 {
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ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c1_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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i2c2 {
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i2c2_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c2";
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ste,pins = "i2c2_b_2";
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};
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default_cfg1 {
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ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c2_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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i2c3 {
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i2c3_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c3";
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ste,pins = "i2c3_c_2";
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};
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default_cfg1 {
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ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c3_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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/*
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* Activating I2C4 will conflict with UART1 about the same pins so do not
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* enable I2C4 and UART1 at the same time.
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*/
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i2c4 {
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i2c4_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c4";
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ste,pins = "i2c4_b_1";
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};
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default_cfg1 {
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ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c4_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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/* Settings for all MMC/SD/SDIO default and sleep states */
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sdi0 {
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/* This is the external SD card slot, 4 bits wide */
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sdi0_default_mode: sdi0_default {
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default_mux {
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ste,function = "mc0";
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ste,pins = "mc0_a_1";
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};
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default_cfg1 {
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ste,pins =
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"GPIO18_AC2", /* CMDDIR */
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"GPIO19_AC1", /* DAT0DIR */
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"GPIO20_AB4"; /* DAT2DIR */
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ste,config = <&out_hi>;
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};
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default_cfg2 {
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ste,pins = "GPIO22_AA3"; /* FBCLK */
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ste,config = <&in_nopull>;
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};
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default_cfg3 {
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ste,pins = "GPIO23_AA4"; /* CLK */
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ste,config = <&out_lo>;
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};
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default_cfg4 {
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ste,pins =
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"GPIO24_AB2", /* CMD */
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"GPIO25_Y4", /* DAT0 */
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"GPIO26_Y2", /* DAT1 */
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"GPIO27_AA2", /* DAT2 */
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"GPIO28_AA1"; /* DAT3 */
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ste,config = <&in_pu>;
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};
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};
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sdi0_sleep_mode: sdi0_sleep {
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sleep_cfg1 {
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ste,pins =
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"GPIO18_AC2", /* CMDDIR */
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"GPIO19_AC1", /* DAT0DIR */
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"GPIO20_AB4"; /* DAT2DIR */
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ste,config = <&slpm_out_hi_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins =
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"GPIO22_AA3", /* FBCLK */
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"GPIO24_AB2", /* CMD */
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"GPIO25_Y4", /* DAT0 */
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"GPIO26_Y2", /* DAT1 */
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"GPIO27_AA2", /* DAT2 */
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"GPIO28_AA1"; /* DAT3 */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg3 {
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ste,pins = "GPIO23_AA4"; /* CLK */
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ste,config = <&slpm_out_lo_wkup_pdis>;
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};
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};
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};
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sdi1 {
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/* This is the WLAN SDIO 4 bits wide */
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sdi1_default_mode: sdi1_default {
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default_mux {
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ste,function = "mc1";
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ste,pins = "mc1_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO208_AH16"; /* CLK */
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ste,config = <&out_lo>;
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};
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default_cfg2 {
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ste,pins = "GPIO209_AG15"; /* FBCLK */
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ste,config = <&in_nopull>;
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};
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default_cfg3 {
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ste,pins =
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"GPIO210_AJ15", /* CMD */
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"GPIO211_AG14", /* DAT0 */
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"GPIO212_AF13", /* DAT1 */
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"GPIO213_AG13", /* DAT2 */
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"GPIO214_AH15"; /* DAT3 */
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ste,config = <&in_pu>;
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};
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};
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sdi1_sleep_mode: sdi1_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO208_AH16"; /* CLK */
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ste,config = <&slpm_out_lo_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins =
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"GPIO209_AG15", /* FBCLK */
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"GPIO210_AJ15", /* CMD */
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"GPIO211_AG14", /* DAT0 */
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"GPIO212_AF13", /* DAT1 */
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"GPIO213_AG13", /* DAT2 */
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"GPIO214_AH15"; /* DAT3 */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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sdi2 {
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/* This is the eMMC 8 bits wide, usually PoP eMMC */
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sdi2_default_mode: sdi2_default {
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default_mux {
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ste,function = "mc2";
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ste,pins = "mc2_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO128_A5"; /* CLK */
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ste,config = <&out_lo>;
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};
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default_cfg2 {
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ste,pins = "GPIO130_C8"; /* FBCLK */
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ste,config = <&in_nopull>;
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};
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default_cfg3 {
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ste,pins =
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"GPIO129_B4", /* CMD */
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"GPIO131_A12", /* DAT0 */
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"GPIO132_C10", /* DAT1 */
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"GPIO133_B10", /* DAT2 */
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"GPIO134_B9", /* DAT3 */
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"GPIO135_A9", /* DAT4 */
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"GPIO136_C7", /* DAT5 */
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"GPIO137_A7", /* DAT6 */
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"GPIO138_C5"; /* DAT7 */
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ste,config = <&in_pu>;
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};
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};
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sdi2_sleep_mode: sdi2_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO128_A5"; /* CLK */
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ste,config = <&out_lo_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins =
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"GPIO130_C8", /* FBCLK */
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"GPIO129_B4"; /* CMD */
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ste,config = <&in_wkup_pdis_en>;
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};
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sleep_cfg3 {
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ste,pins =
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"GPIO131_A12", /* DAT0 */
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"GPIO132_C10", /* DAT1 */
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"GPIO133_B10", /* DAT2 */
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"GPIO134_B9", /* DAT3 */
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"GPIO135_A9", /* DAT4 */
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"GPIO136_C7", /* DAT5 */
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"GPIO137_A7", /* DAT6 */
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"GPIO138_C5"; /* DAT7 */
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ste,config = <&in_wkup_pdis>;
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};
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};
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};
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sdi4 {
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/* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
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sdi4_default_mode: sdi4_default {
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default_mux {
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ste,function = "mc4";
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ste,pins = "mc4_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO203_AE23"; /* CLK */
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ste,config = <&out_lo>;
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};
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default_cfg2 {
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ste,pins = "GPIO202_AF25"; /* FBCLK */
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ste,config = <&in_nopull>;
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};
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default_cfg3 {
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ste,pins =
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"GPIO201_AF24", /* CMD */
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"GPIO200_AH26", /* DAT0 */
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"GPIO199_AH23", /* DAT1 */
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"GPIO198_AG25", /* DAT2 */
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"GPIO197_AH24", /* DAT3 */
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"GPIO207_AJ23", /* DAT4 */
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"GPIO206_AG24", /* DAT5 */
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"GPIO205_AG23", /* DAT6 */
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"GPIO204_AF23"; /* DAT7 */
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ste,config = <&in_pu>;
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};
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};
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sdi4_sleep_mode: sdi4_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO203_AE23"; /* CLK */
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ste,config = <&out_lo_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins =
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"GPIO202_AF25", /* FBCLK */
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"GPIO201_AF24", /* CMD */
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"GPIO200_AH26", /* DAT0 */
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"GPIO199_AH23", /* DAT1 */
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"GPIO198_AG25", /* DAT2 */
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"GPIO197_AH24", /* DAT3 */
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"GPIO207_AJ23", /* DAT4 */
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"GPIO206_AG24", /* DAT5 */
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"GPIO205_AG23", /* DAT6 */
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"GPIO204_AF23"; /* DAT7 */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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};
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};
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};
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