forked from Minki/linux
1db6de22b2
Let general names to core drivers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
550 lines
16 KiB
C
550 lines
16 KiB
C
/*
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* Driver for Atmel QSPI Controller
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*
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* Copyright (C) 2015 Atmel Corporation
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* Copyright (C) 2018 Cryptera A/S
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*
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* Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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* Author: Piotr Bugalski <bugalski.piotr@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi-mem.h>
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/* QSPI register offsets */
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#define QSPI_CR 0x0000 /* Control Register */
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#define QSPI_MR 0x0004 /* Mode Register */
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#define QSPI_RD 0x0008 /* Receive Data Register */
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#define QSPI_TD 0x000c /* Transmit Data Register */
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#define QSPI_SR 0x0010 /* Status Register */
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#define QSPI_IER 0x0014 /* Interrupt Enable Register */
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#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
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#define QSPI_IMR 0x001c /* Interrupt Mask Register */
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#define QSPI_SCR 0x0020 /* Serial Clock Register */
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#define QSPI_IAR 0x0030 /* Instruction Address Register */
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#define QSPI_ICR 0x0034 /* Instruction Code Register */
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#define QSPI_IFR 0x0038 /* Instruction Frame Register */
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#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
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#define QSPI_SKR 0x0044 /* Scrambling Key Register */
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#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
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#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
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#define QSPI_VERSION 0x00FC /* Version Register */
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/* Bitfields in QSPI_CR (Control Register) */
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#define QSPI_CR_QSPIEN BIT(0)
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#define QSPI_CR_QSPIDIS BIT(1)
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#define QSPI_CR_SWRST BIT(7)
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#define QSPI_CR_LASTXFER BIT(24)
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/* Bitfields in QSPI_MR (Mode Register) */
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#define QSPI_MR_SMM BIT(0)
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#define QSPI_MR_LLB BIT(1)
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#define QSPI_MR_WDRBT BIT(2)
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#define QSPI_MR_SMRM BIT(3)
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#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
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#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
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#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
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#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
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#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
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#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
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#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
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#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
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#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
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#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
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/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
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#define QSPI_SR_RDRF BIT(0)
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#define QSPI_SR_TDRE BIT(1)
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#define QSPI_SR_TXEMPTY BIT(2)
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#define QSPI_SR_OVRES BIT(3)
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#define QSPI_SR_CSR BIT(8)
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#define QSPI_SR_CSS BIT(9)
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#define QSPI_SR_INSTRE BIT(10)
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#define QSPI_SR_QSPIENS BIT(24)
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#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
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/* Bitfields in QSPI_SCR (Serial Clock Register) */
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#define QSPI_SCR_CPOL BIT(0)
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#define QSPI_SCR_CPHA BIT(1)
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#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
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#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
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#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
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#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
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/* Bitfields in QSPI_ICR (Instruction Code Register) */
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#define QSPI_ICR_INST_MASK GENMASK(7, 0)
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#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
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#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
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#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
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/* Bitfields in QSPI_IFR (Instruction Frame Register) */
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#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
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#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
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#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
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#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
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#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
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#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
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#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
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#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
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#define QSPI_IFR_INSTEN BIT(4)
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#define QSPI_IFR_ADDREN BIT(5)
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#define QSPI_IFR_OPTEN BIT(6)
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#define QSPI_IFR_DATAEN BIT(7)
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#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
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#define QSPI_IFR_OPTL_1BIT (0 << 8)
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#define QSPI_IFR_OPTL_2BIT (1 << 8)
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#define QSPI_IFR_OPTL_4BIT (2 << 8)
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#define QSPI_IFR_OPTL_8BIT (3 << 8)
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#define QSPI_IFR_ADDRL BIT(10)
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#define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12)
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#define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12)
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#define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12)
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#define QSPI_IFR_TFRTYP_TRSFR_WRITE (2 << 12)
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#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13)
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#define QSPI_IFR_CRM BIT(14)
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#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
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#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
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/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
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#define QSPI_SMR_SCREN BIT(0)
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#define QSPI_SMR_RVDIS BIT(1)
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/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
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#define QSPI_WPMR_WPEN BIT(0)
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#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
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#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
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/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
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#define QSPI_WPSR_WPVS BIT(0)
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#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
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#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
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struct atmel_qspi {
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void __iomem *regs;
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void __iomem *mem;
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struct clk *clk;
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struct platform_device *pdev;
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u32 pending;
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u32 mr;
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struct completion cmd_completion;
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};
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struct atmel_qspi_mode {
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u8 cmd_buswidth;
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u8 addr_buswidth;
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u8 data_buswidth;
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u32 config;
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};
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static const struct atmel_qspi_mode sama5d2_qspi_modes[] = {
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{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
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{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
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{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
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{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
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{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
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{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
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{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
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};
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static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
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const struct atmel_qspi_mode *mode)
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{
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if (op->cmd.buswidth != mode->cmd_buswidth)
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return false;
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if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
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return false;
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if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
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return false;
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return true;
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}
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static int atmel_qspi_find_mode(const struct spi_mem_op *op)
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{
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u32 i;
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for (i = 0; i < ARRAY_SIZE(sama5d2_qspi_modes); i++)
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if (atmel_qspi_is_compatible(op, &sama5d2_qspi_modes[i]))
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return i;
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return -1;
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}
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static bool atmel_qspi_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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if (atmel_qspi_find_mode(op) < 0)
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return false;
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/* special case not supported by hardware */
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if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
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op->dummy.nbytes == 0)
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return false;
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return true;
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}
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static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
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int mode;
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u32 dummy_cycles = 0;
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u32 iar, icr, ifr, sr;
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int err = 0;
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iar = 0;
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icr = QSPI_ICR_INST(op->cmd.opcode);
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ifr = QSPI_IFR_INSTEN;
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/*
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* If the QSPI controller is set in regular SPI mode, set it in
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* Serial Memory Mode (SMM).
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*/
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if (aq->mr != QSPI_MR_SMM) {
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writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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}
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mode = atmel_qspi_find_mode(op);
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if (mode < 0)
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return -ENOTSUPP;
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ifr |= sama5d2_qspi_modes[mode].config;
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if (op->dummy.buswidth && op->dummy.nbytes)
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dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
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if (op->addr.buswidth) {
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switch (op->addr.nbytes) {
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case 0:
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break;
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case 1:
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ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
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icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
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break;
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case 2:
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if (dummy_cycles < 8 / op->addr.buswidth) {
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ifr &= ~QSPI_IFR_INSTEN;
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ifr |= QSPI_IFR_ADDREN;
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iar = (op->cmd.opcode << 16) |
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(op->addr.val & 0xffff);
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} else {
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ifr |= QSPI_IFR_ADDREN;
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iar = (op->addr.val << 8) & 0xffffff;
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dummy_cycles -= 8 / op->addr.buswidth;
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}
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break;
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case 3:
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ifr |= QSPI_IFR_ADDREN;
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iar = op->addr.val & 0xffffff;
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break;
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case 4:
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ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
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iar = op->addr.val & 0x7ffffff;
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break;
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default:
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return -ENOTSUPP;
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}
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}
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/* Set number of dummy cycles */
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if (dummy_cycles)
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ifr |= QSPI_IFR_NBDUM(dummy_cycles);
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/* Set data enable */
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if (op->data.nbytes)
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ifr |= QSPI_IFR_DATAEN;
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if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
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ifr |= QSPI_IFR_TFRTYP_TRSFR_READ;
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else
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ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE;
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/* Clear pending interrupts */
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(void)readl_relaxed(aq->regs + QSPI_SR);
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/* Set QSPI Instruction Frame registers */
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writel_relaxed(iar, aq->regs + QSPI_IAR);
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writel_relaxed(icr, aq->regs + QSPI_ICR);
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writel_relaxed(ifr, aq->regs + QSPI_IFR);
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/* Skip to the final steps if there is no data */
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if (op->data.nbytes) {
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/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
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(void)readl_relaxed(aq->regs + QSPI_IFR);
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/* Send/Receive data */
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if (op->data.dir == SPI_MEM_DATA_IN)
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_memcpy_fromio(op->data.buf.in,
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aq->mem + iar, op->data.nbytes);
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else
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_memcpy_toio(aq->mem + iar,
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op->data.buf.out, op->data.nbytes);
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/* Release the chip-select */
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writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
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}
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/* Poll INSTRuction End status */
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sr = readl_relaxed(aq->regs + QSPI_SR);
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if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
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return err;
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/* Wait for INSTRuction End interrupt */
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reinit_completion(&aq->cmd_completion);
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aq->pending = sr & QSPI_SR_CMD_COMPLETED;
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writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
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if (!wait_for_completion_timeout(&aq->cmd_completion,
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msecs_to_jiffies(1000)))
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err = -ETIMEDOUT;
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writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);
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return err;
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}
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const char *atmel_qspi_get_name(struct spi_mem *spimem)
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{
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return dev_name(spimem->spi->dev.parent);
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}
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static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
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.supports_op = atmel_qspi_supports_op,
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.exec_op = atmel_qspi_exec_op,
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.get_name = atmel_qspi_get_name
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};
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static int atmel_qspi_setup(struct spi_device *spi)
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{
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struct spi_controller *ctrl = spi->master;
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struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
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unsigned long src_rate;
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u32 scr, scbr;
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if (ctrl->busy)
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return -EBUSY;
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if (!spi->max_speed_hz)
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return -EINVAL;
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src_rate = clk_get_rate(aq->clk);
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if (!src_rate)
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return -EINVAL;
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/* Compute the QSPI baudrate */
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scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
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if (scbr > 0)
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scbr--;
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scr = QSPI_SCR_SCBR(scbr);
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writel_relaxed(scr, aq->regs + QSPI_SCR);
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return 0;
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}
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static int atmel_qspi_init(struct atmel_qspi *aq)
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{
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/* Reset the QSPI controller */
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writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);
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/* Set the QSPI controller by default in Serial Memory Mode */
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writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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/* Enable the QSPI controller */
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writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
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return 0;
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}
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static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
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{
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struct atmel_qspi *aq = (struct atmel_qspi *)dev_id;
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u32 status, mask, pending;
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status = readl_relaxed(aq->regs + QSPI_SR);
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mask = readl_relaxed(aq->regs + QSPI_IMR);
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pending = status & mask;
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if (!pending)
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return IRQ_NONE;
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aq->pending |= pending;
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if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
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complete(&aq->cmd_completion);
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return IRQ_HANDLED;
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}
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static int atmel_qspi_probe(struct platform_device *pdev)
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{
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struct spi_controller *ctrl;
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struct atmel_qspi *aq;
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struct resource *res;
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int irq, err = 0;
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ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
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if (!ctrl)
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return -ENOMEM;
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ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
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ctrl->setup = atmel_qspi_setup;
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ctrl->bus_num = -1;
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ctrl->mem_ops = &atmel_qspi_mem_ops;
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ctrl->num_chipselect = 1;
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ctrl->dev.of_node = pdev->dev.of_node;
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platform_set_drvdata(pdev, ctrl);
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aq = spi_controller_get_devdata(ctrl);
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init_completion(&aq->cmd_completion);
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aq->pdev = pdev;
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/* Map the registers */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
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aq->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(aq->regs)) {
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dev_err(&pdev->dev, "missing registers\n");
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err = PTR_ERR(aq->regs);
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goto exit;
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}
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/* Map the AHB memory */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
|
|
aq->mem = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(aq->mem)) {
|
|
dev_err(&pdev->dev, "missing AHB memory\n");
|
|
err = PTR_ERR(aq->mem);
|
|
goto exit;
|
|
}
|
|
|
|
/* Get the peripheral clock */
|
|
aq->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(aq->clk)) {
|
|
dev_err(&pdev->dev, "missing peripheral clock\n");
|
|
err = PTR_ERR(aq->clk);
|
|
goto exit;
|
|
}
|
|
|
|
/* Enable the peripheral clock */
|
|
err = clk_prepare_enable(aq->clk);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
|
|
goto exit;
|
|
}
|
|
|
|
/* Request the IRQ */
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "missing IRQ\n");
|
|
err = irq;
|
|
goto disable_clk;
|
|
}
|
|
err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
|
|
0, dev_name(&pdev->dev), aq);
|
|
if (err)
|
|
goto disable_clk;
|
|
|
|
err = atmel_qspi_init(aq);
|
|
if (err)
|
|
goto disable_clk;
|
|
|
|
err = spi_register_controller(ctrl);
|
|
if (err)
|
|
goto disable_clk;
|
|
|
|
return 0;
|
|
|
|
disable_clk:
|
|
clk_disable_unprepare(aq->clk);
|
|
exit:
|
|
spi_controller_put(ctrl);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int atmel_qspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_controller *ctrl = platform_get_drvdata(pdev);
|
|
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
|
|
|
|
spi_unregister_controller(ctrl);
|
|
writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
|
|
clk_disable_unprepare(aq->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused atmel_qspi_suspend(struct device *dev)
|
|
{
|
|
struct atmel_qspi *aq = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(aq->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused atmel_qspi_resume(struct device *dev)
|
|
{
|
|
struct atmel_qspi *aq = dev_get_drvdata(dev);
|
|
|
|
clk_prepare_enable(aq->clk);
|
|
|
|
return atmel_qspi_init(aq);
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
|
|
atmel_qspi_resume);
|
|
|
|
static const struct of_device_id atmel_qspi_dt_ids[] = {
|
|
{ .compatible = "atmel,sama5d2-qspi" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
|
|
|
|
static struct platform_driver atmel_qspi_driver = {
|
|
.driver = {
|
|
.name = "atmel_qspi",
|
|
.of_match_table = atmel_qspi_dt_ids,
|
|
.pm = &atmel_qspi_pm_ops,
|
|
},
|
|
.probe = atmel_qspi_probe,
|
|
.remove = atmel_qspi_remove,
|
|
};
|
|
module_platform_driver(atmel_qspi_driver);
|
|
|
|
MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
|
|
MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
|
|
MODULE_DESCRIPTION("Atmel QSPI Controller driver");
|
|
MODULE_LICENSE("GPL v2");
|