d360892d37
On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10, 131, 132, 133 are direct wired to hardware blocks bypassing crossbar. This quirky implementation is *NOT* supposed to be the expectation of crossbar hardware usage. However, these are already marked in our description of the hardware with SKIP and RESERVED where appropriate. Unfortunately, we need to be able to refer to these hardwired IRQs. So, to request these, crossbar driver can use the existing information from it's table that these SKIP/RESERVED maps are direct wired sources and generic allocation/programming of crossbar should be avoided. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Link: https://lkml.kernel.org/r/1403766634-18543-17-git-send-email-r.sricharan@ti.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
64 lines
2.4 KiB
Plaintext
64 lines
2.4 KiB
Plaintext
Some socs have a large number of interrupts requests to service
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the needs of its many peripherals and subsystems. All of the
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interrupt lines from the subsystems are not needed at the same
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time, so they have to be muxed to the irq-controller appropriately.
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In such places a interrupt controllers are preceded by an CROSSBAR
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that provides flexibility in muxing the device requests to the controller
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inputs.
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Required properties:
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- compatible : Should be "ti,irq-crossbar"
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- reg: Base address and the size of the crossbar registers.
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- ti,max-irqs: Total number of irqs available at the interrupt controller.
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- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
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- ti,reg-size: Size of a individual register in bytes. Every individual
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register is assumed to be of same size. Valid sizes are 1, 2, 4.
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- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
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crossbar. These interrupt lines are reserved in the soc,
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so crossbar bar driver should not consider them as free
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lines.
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Optional properties:
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- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
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SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
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crossbar. These irqs have a crossbar register, but still cannot be used.
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- ti,irqs-safe-map: integer which maps to a safe configuration to use
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when the interrupt controller irq is unused (when not provided, default is 0)
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Examples:
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crossbar_mpu: @4a020000 {
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compatible = "ti,irq-crossbar";
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reg = <0x4a002a48 0x130>;
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ti,max-irqs = <160>;
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ti,max-crossbar-sources = <400>;
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ti,reg-size = <2>;
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ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
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ti,irqs-skip = <10 133 139 140>;
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};
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Consumer:
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========
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See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
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Documentation/devicetree/bindings/arm/gic.txt for further details.
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An interrupt consumer on an SoC using crossbar will use:
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interrupts = <GIC_SPI request_number interrupt_level>
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When the request number is between 0 to that described by
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"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
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request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
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quirky hardware mapping direct to GIC.
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Example:
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device_x@0x4a023000 {
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/* Crossbar 8 used */
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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...
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};
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device_y@0x4a033000 {
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/* Direct mapped GIC SPI 1 used */
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interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
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...
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};
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