395b23ca57
DRA7 Data Manual (SPRS857L - August 2014) section 4.1.1 states: "All unused power supply balls must be supplied with the voltages specified in the Section 5.2, Recommended Operating Conditions". This implies that all unused voltage rails for Vayu can never be switched off even if the hardware blocks inside that voltage domain is unused. Switching off these unused rails may result in stability issues on other domains and increased leakage and power-on-hour impacts. J6eco-evm dts file already considers this, however j6evm-dts file needs to be fixed to consider this constraint of the SoC. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
642 lines
16 KiB
Plaintext
642 lines
16 KiB
Plaintext
/*
|
|
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
#include "dra74x.dtsi"
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
/ {
|
|
model = "TI DRA742";
|
|
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x80000000 0x60000000>; /* 1536 MB */
|
|
};
|
|
|
|
mmc2_3v3: fixedregulator-mmc2 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "mmc2_3v3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
vtt_fixed: fixedregulator-vtt {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vtt_fixed";
|
|
regulator-min-microvolt = <1350000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
enable-active-high;
|
|
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
|
|
&dra7_pmx_core {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&vtt_pin>;
|
|
|
|
vtt_pin: pinmux_vtt_pin {
|
|
pinctrl-single,pins = <
|
|
0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
|
|
>;
|
|
};
|
|
|
|
i2c1_pins: pinmux_i2c1_pins {
|
|
pinctrl-single,pins = <
|
|
0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
|
|
0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
|
|
>;
|
|
};
|
|
|
|
i2c2_pins: pinmux_i2c2_pins {
|
|
pinctrl-single,pins = <
|
|
0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
|
|
0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
|
|
>;
|
|
};
|
|
|
|
i2c3_pins: pinmux_i2c3_pins {
|
|
pinctrl-single,pins = <
|
|
0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
|
|
0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
|
|
>;
|
|
};
|
|
|
|
mcspi1_pins: pinmux_mcspi1_pins {
|
|
pinctrl-single,pins = <
|
|
0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
|
|
0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
|
|
0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
|
|
0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
|
|
0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
|
|
0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
|
|
>;
|
|
};
|
|
|
|
mcspi2_pins: pinmux_mcspi2_pins {
|
|
pinctrl-single,pins = <
|
|
0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
|
|
0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
|
|
0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
|
|
0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
|
|
>;
|
|
};
|
|
|
|
uart1_pins: pinmux_uart1_pins {
|
|
pinctrl-single,pins = <
|
|
0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
|
|
0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
|
|
0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
|
|
0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
|
|
>;
|
|
};
|
|
|
|
uart2_pins: pinmux_uart2_pins {
|
|
pinctrl-single,pins = <
|
|
0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
|
|
0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
|
|
0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
|
|
0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
|
|
>;
|
|
};
|
|
|
|
uart3_pins: pinmux_uart3_pins {
|
|
pinctrl-single,pins = <
|
|
0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
|
|
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
|
|
>;
|
|
};
|
|
|
|
qspi1_pins: pinmux_qspi1_pins {
|
|
pinctrl-single,pins = <
|
|
0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
|
|
0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
|
|
0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
|
|
0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
|
|
0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
|
|
0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
|
|
0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
|
|
0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
|
|
0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
|
|
0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
|
|
>;
|
|
};
|
|
|
|
usb1_pins: pinmux_usb1_pins {
|
|
pinctrl-single,pins = <
|
|
0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
|
|
>;
|
|
};
|
|
|
|
usb2_pins: pinmux_usb2_pins {
|
|
pinctrl-single,pins = <
|
|
0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
|
|
>;
|
|
};
|
|
|
|
nand_flash_x16: nand_flash_x16 {
|
|
/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
|
|
* So NAND flash requires following switch settings:
|
|
* SW5.9 (GPMC_WPN) = LOW
|
|
* SW5.1 (NAND_BOOTn) = HIGH */
|
|
pinctrl-single,pins = <
|
|
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
|
|
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
|
|
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
|
|
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
|
|
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
|
|
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
|
|
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
|
|
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
|
|
0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
|
|
0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
|
|
0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
|
|
0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
|
|
0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
|
|
0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
|
|
0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
|
|
0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
|
|
0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
|
|
0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
|
|
0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
|
|
0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
|
|
0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
|
|
0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
|
|
>;
|
|
};
|
|
|
|
cpsw_default: cpsw_default {
|
|
pinctrl-single,pins = <
|
|
/* Slave 1 */
|
|
0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
|
|
0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
|
|
0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
|
|
0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
|
|
0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
|
|
0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
|
|
0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
|
|
0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
|
|
0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
|
|
0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
|
|
0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
|
|
0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
|
|
|
|
/* Slave 2 */
|
|
0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
|
|
0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
|
|
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
|
|
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
|
|
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
|
|
0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
|
|
0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
|
|
0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
|
|
0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
|
|
0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
|
|
0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
|
|
0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
|
|
>;
|
|
|
|
};
|
|
|
|
cpsw_sleep: cpsw_sleep {
|
|
pinctrl-single,pins = <
|
|
/* Slave 1 */
|
|
0x250 (MUX_MODE15)
|
|
0x254 (MUX_MODE15)
|
|
0x258 (MUX_MODE15)
|
|
0x25c (MUX_MODE15)
|
|
0x260 (MUX_MODE15)
|
|
0x264 (MUX_MODE15)
|
|
0x268 (MUX_MODE15)
|
|
0x26c (MUX_MODE15)
|
|
0x270 (MUX_MODE15)
|
|
0x274 (MUX_MODE15)
|
|
0x278 (MUX_MODE15)
|
|
0x27c (MUX_MODE15)
|
|
|
|
/* Slave 2 */
|
|
0x198 (MUX_MODE15)
|
|
0x19c (MUX_MODE15)
|
|
0x1a0 (MUX_MODE15)
|
|
0x1a4 (MUX_MODE15)
|
|
0x1a8 (MUX_MODE15)
|
|
0x1ac (MUX_MODE15)
|
|
0x1b0 (MUX_MODE15)
|
|
0x1b4 (MUX_MODE15)
|
|
0x1b8 (MUX_MODE15)
|
|
0x1bc (MUX_MODE15)
|
|
0x1c0 (MUX_MODE15)
|
|
0x1c4 (MUX_MODE15)
|
|
>;
|
|
};
|
|
|
|
davinci_mdio_default: davinci_mdio_default {
|
|
pinctrl-single,pins = <
|
|
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
|
|
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
|
>;
|
|
};
|
|
|
|
davinci_mdio_sleep: davinci_mdio_sleep {
|
|
pinctrl-single,pins = <
|
|
0x23c (MUX_MODE15)
|
|
0x240 (MUX_MODE15)
|
|
>;
|
|
};
|
|
|
|
};
|
|
|
|
&i2c1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_pins>;
|
|
clock-frequency = <400000>;
|
|
|
|
tps659038: tps659038@58 {
|
|
compatible = "ti,tps659038";
|
|
reg = <0x58>;
|
|
|
|
tps659038_pmic {
|
|
compatible = "ti,tps659038-pmic";
|
|
|
|
regulators {
|
|
smps123_reg: smps123 {
|
|
/* VDD_MPU */
|
|
regulator-name = "smps123";
|
|
regulator-min-microvolt = < 850000>;
|
|
regulator-max-microvolt = <1250000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
smps45_reg: smps45 {
|
|
/* VDD_DSPEVE */
|
|
regulator-name = "smps45";
|
|
regulator-min-microvolt = < 850000>;
|
|
regulator-max-microvolt = <1150000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
smps6_reg: smps6 {
|
|
/* VDD_GPU - over VDD_SMPS6 */
|
|
regulator-name = "smps6";
|
|
regulator-min-microvolt = <850000>;
|
|
regulator-max-microvolt = <12500000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
smps7_reg: smps7 {
|
|
/* CORE_VDD */
|
|
regulator-name = "smps7";
|
|
regulator-min-microvolt = <850000>;
|
|
regulator-max-microvolt = <1030000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
smps8_reg: smps8 {
|
|
/* VDD_IVAHD */
|
|
regulator-name = "smps8";
|
|
regulator-min-microvolt = < 850000>;
|
|
regulator-max-microvolt = <1250000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
smps9_reg: smps9 {
|
|
/* VDDS1V8 */
|
|
regulator-name = "smps9";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldo1_reg: ldo1 {
|
|
/* LDO1_OUT --> SDIO */
|
|
regulator-name = "ldo1";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldo2_reg: ldo2 {
|
|
/* VDD_RTCIO */
|
|
/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
|
|
regulator-name = "ldo2";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldo3_reg: ldo3 {
|
|
/* VDDA_1V8_PHY */
|
|
regulator-name = "ldo3";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldo9_reg: ldo9 {
|
|
/* VDD_RTC */
|
|
regulator-name = "ldo9";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldoln_reg: ldoln {
|
|
/* VDDA_1V8_PLL */
|
|
regulator-name = "ldoln";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldousb_reg: ldousb {
|
|
/* VDDA_3V_USB: VDDA_USBHS33 */
|
|
regulator-name = "ldousb";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c2 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_pins>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
&i2c3 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_pins>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
&mcspi1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcspi1_pins>;
|
|
};
|
|
|
|
&mcspi2 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcspi2_pins>;
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_pins>;
|
|
interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&dra7_pmx_core 0x3e0>;
|
|
};
|
|
|
|
&uart2 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_pins>;
|
|
};
|
|
|
|
&uart3 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_pins>;
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
vmmc-supply = <&ldo1_reg>;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
&mmc2 {
|
|
status = "okay";
|
|
vmmc-supply = <&mmc2_3v3>;
|
|
bus-width = <8>;
|
|
};
|
|
|
|
&cpu0 {
|
|
cpu0-supply = <&smps123_reg>;
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qspi1_pins>;
|
|
|
|
spi-max-frequency = <48000000>;
|
|
m25p80@0 {
|
|
compatible = "s25fl256s1";
|
|
spi-max-frequency = <48000000>;
|
|
reg = <0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>;
|
|
spi-cpol;
|
|
spi-cpha;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/* MTD partition table.
|
|
* The ROM checks the first four physical blocks
|
|
* for a valid file to boot and the flash here is
|
|
* 64KiB block size.
|
|
*/
|
|
partition@0 {
|
|
label = "QSPI.SPL";
|
|
reg = <0x00000000 0x000010000>;
|
|
};
|
|
partition@1 {
|
|
label = "QSPI.SPL.backup1";
|
|
reg = <0x00010000 0x00010000>;
|
|
};
|
|
partition@2 {
|
|
label = "QSPI.SPL.backup2";
|
|
reg = <0x00020000 0x00010000>;
|
|
};
|
|
partition@3 {
|
|
label = "QSPI.SPL.backup3";
|
|
reg = <0x00030000 0x00010000>;
|
|
};
|
|
partition@4 {
|
|
label = "QSPI.u-boot";
|
|
reg = <0x00040000 0x00100000>;
|
|
};
|
|
partition@5 {
|
|
label = "QSPI.u-boot-spl-os";
|
|
reg = <0x00140000 0x00010000>;
|
|
};
|
|
partition@6 {
|
|
label = "QSPI.u-boot-env";
|
|
reg = <0x00150000 0x00010000>;
|
|
};
|
|
partition@7 {
|
|
label = "QSPI.u-boot-env.backup1";
|
|
reg = <0x00160000 0x0010000>;
|
|
};
|
|
partition@8 {
|
|
label = "QSPI.kernel";
|
|
reg = <0x00170000 0x0800000>;
|
|
};
|
|
partition@9 {
|
|
label = "QSPI.file-system";
|
|
reg = <0x00970000 0x01690000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb1 {
|
|
dr_mode = "peripheral";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb1_pins>;
|
|
};
|
|
|
|
&usb2 {
|
|
dr_mode = "host";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb2_pins>;
|
|
};
|
|
|
|
&elm {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpmc {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&nand_flash_x16>;
|
|
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
|
nand@0,0 {
|
|
reg = <0 0 4>; /* device IO registers */
|
|
ti,nand-ecc-opt = "bch8";
|
|
ti,elm-id = <&elm>;
|
|
nand-bus-width = <16>;
|
|
gpmc,device-width = <2>;
|
|
gpmc,sync-clk-ps = <0>;
|
|
gpmc,cs-on-ns = <0>;
|
|
gpmc,cs-rd-off-ns = <80>;
|
|
gpmc,cs-wr-off-ns = <80>;
|
|
gpmc,adv-on-ns = <0>;
|
|
gpmc,adv-rd-off-ns = <60>;
|
|
gpmc,adv-wr-off-ns = <60>;
|
|
gpmc,we-on-ns = <10>;
|
|
gpmc,we-off-ns = <50>;
|
|
gpmc,oe-on-ns = <4>;
|
|
gpmc,oe-off-ns = <40>;
|
|
gpmc,access-ns = <40>;
|
|
gpmc,wr-access-ns = <80>;
|
|
gpmc,rd-cycle-ns = <80>;
|
|
gpmc,wr-cycle-ns = <80>;
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
gpmc,clk-activation-ns = <0>;
|
|
gpmc,wait-monitoring-ns = <0>;
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
/* MTD partition table */
|
|
/* All SPL-* partitions are sized to minimal length
|
|
* which can be independently programmable. For
|
|
* NAND flash this is equal to size of erase-block */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
partition@0 {
|
|
label = "NAND.SPL";
|
|
reg = <0x00000000 0x000020000>;
|
|
};
|
|
partition@1 {
|
|
label = "NAND.SPL.backup1";
|
|
reg = <0x00020000 0x00020000>;
|
|
};
|
|
partition@2 {
|
|
label = "NAND.SPL.backup2";
|
|
reg = <0x00040000 0x00020000>;
|
|
};
|
|
partition@3 {
|
|
label = "NAND.SPL.backup3";
|
|
reg = <0x00060000 0x00020000>;
|
|
};
|
|
partition@4 {
|
|
label = "NAND.u-boot-spl-os";
|
|
reg = <0x00080000 0x00040000>;
|
|
};
|
|
partition@5 {
|
|
label = "NAND.u-boot";
|
|
reg = <0x000c0000 0x00100000>;
|
|
};
|
|
partition@6 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x001c0000 0x00020000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env.backup1";
|
|
reg = <0x001e0000 0x00020000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00200000 0x00800000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00a00000 0x0f600000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb2_phy1 {
|
|
phy-supply = <&ldousb_reg>;
|
|
};
|
|
|
|
&usb2_phy2 {
|
|
phy-supply = <&ldousb_reg>;
|
|
};
|
|
|
|
&gpio7 {
|
|
ti,no-reset-on-init;
|
|
ti,no-idle-on-init;
|
|
};
|
|
|
|
&mac {
|
|
status = "okay";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&cpsw_default>;
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
dual_emac;
|
|
};
|
|
|
|
&cpsw_emac0 {
|
|
phy_id = <&davinci_mdio>, <2>;
|
|
phy-mode = "rgmii";
|
|
dual_emac_res_vlan = <1>;
|
|
};
|
|
|
|
&cpsw_emac1 {
|
|
phy_id = <&davinci_mdio>, <3>;
|
|
phy-mode = "rgmii";
|
|
dual_emac_res_vlan = <2>;
|
|
};
|
|
|
|
&davinci_mdio {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
};
|