Chris Zhong 1d33929e2a clk: rockchip: switch PLLs to slow mode before reboot for rk3288 ... We've been seeing some crashes at reboot test on rk3288-based systems, which boards have not reset pin connected to NPOR, they reboot by setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in a high frequency mode, some IPs might hang during soft reset. It appears that we can fix the problem by switching to slow mode before reboot, just like what we did before suspend. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2015-12-01 18:33:43 +01:00
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clk-cpu.c	clk: rockchip: Properly include clk.h	2015-07-20 11:11:10 -07:00
clk-inverter.c	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	2015-08-24 16:49:12 -07:00
clk-mmc-phase.c	The majority of the changes are driver updates and new device	2015-11-05 12:59:36 -08:00
clk-pll.c	clk: rockchip: add new pll-type for rk3036 and similar socs	2015-11-23 21:55:07 +01:00
clk-rk3036.c	clk: rockchip: add clock controller for rk3036	2015-11-23 21:59:19 +01:00
clk-rk3188.c	clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188	2015-09-10 13:55:30 -07:00
clk-rk3288.c	clk: rockchip: switch PLLs to slow mode before reboot for rk3288	2015-12-01 18:33:43 +01:00
clk-rk3368.c	clk: rockchip: add critical clock for rk3368	2015-09-14 12:49:39 -07:00
clk-rockchip.c
clk.c	clk: rockchip: save width in struct clk_fractional_divider	2015-10-02 11:29:47 -07:00
clk.h	clk: rockchip: add clock controller for rk3036	2015-11-23 21:59:19 +01:00
Makefile	clk: rockchip: add clock controller for rk3036	2015-11-23 21:59:19 +01:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00