forked from Minki/linux
b78ac6ecd1
Allow the configuration of the MDIO clock divider when the Device Tree contains 'clock-frequency' property (similar to I2C and SPI buses). Because the hardware may have lost its state during suspend/resume, re-apply the MDIO clock divider upon resumption. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
44 lines
1.6 KiB
Plaintext
44 lines
1.6 KiB
Plaintext
* Broadcom UniMAC MDIO bus controller
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Required properties:
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- compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2",
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"brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5" or
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"brcm,unimac-mdio"
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- reg: address and length of the register set for the device, first one is the
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base register, and the second one is optional and for indirect accesses to
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larger than 16-bits MDIO transactions
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- reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
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- #size-cells: must be 1
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- #address-cells: must be 0
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Optional properties:
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- interrupts: must be one if the interrupt is shared with the Ethernet MAC or
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Ethernet switch this MDIO block is integrated from, or must be two, if there
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are two separate interrupts, first one must be "mdio done" and second must be
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for "mdio error"
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- interrupt-names: must be "mdio_done_error" when there is a share interrupt fed
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to this hardware block, or must be "mdio_done" for the first interrupt and
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"mdio_error" for the second when there are separate interrupts
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- clocks: A reference to the clock supplying the MDIO bus controller
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- clock-frequency: the MDIO bus clock that must be output by the MDIO bus
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hardware, if absent, the default hardware values are used
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Child nodes of this MDIO bus controller node are standard Ethernet PHY device
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nodes as described in Documentation/devicetree/bindings/net/phy.txt
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Example:
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mdio@403c0 {
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compatible = "brcm,unimac-mdio";
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reg = <0x403c0 0x8 0x40300 0x18>;
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reg-names = "mdio", "mdio_indir_rw";
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#size-cells = <1>;
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#address-cells = <0>;
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...
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phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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