forked from Minki/linux
ef89af1f43
The customers may want to adjust the whole PLL and dividers according to different user scenerios, and this causes the parent clock of sirf clocksource not be divided exactly by the current hard-coded 1MHz clock rate. This patch removes the hard-coded rate and makes the clocksource driver more adaptive to the external changes. Signed-off-by: Yanchang Li <yl22@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
308 lines
8.7 KiB
C
308 lines
8.7 KiB
C
/*
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* System timer for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/cpu.h>
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/sched_clock.h>
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#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
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#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
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#define SIRFSOC_TIMER_MATCH_0 0x0018
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#define SIRFSOC_TIMER_MATCH_1 0x001c
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#define SIRFSOC_TIMER_COUNTER_0 0x0048
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#define SIRFSOC_TIMER_COUNTER_1 0x004c
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#define SIRFSOC_TIMER_INTR_STATUS 0x0060
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#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
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#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
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#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
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#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
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#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
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#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
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#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
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#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
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#define SIRFSOC_TIMER_REG_CNT 6
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static unsigned long marco_timer_rate;
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static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
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SIRFSOC_TIMER_WATCHDOG_EN,
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SIRFSOC_TIMER_32COUNTER_0_CTRL,
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SIRFSOC_TIMER_32COUNTER_1_CTRL,
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SIRFSOC_TIMER_64COUNTER_CTRL,
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SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
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SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
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};
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static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
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static void __iomem *sirfsoc_timer_base;
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/* disable count and interrupt */
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static inline void sirfsoc_timer_count_disable(int idx)
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{
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writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
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sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
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}
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/* enable count and interrupt */
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static inline void sirfsoc_timer_count_enable(int idx)
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{
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writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
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sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
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}
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/* timer interrupt handler */
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static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *ce = dev_id;
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int cpu = smp_processor_id();
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/* clear timer interrupt */
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writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
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if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
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sirfsoc_timer_count_disable(cpu);
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ce->event_handler(ce);
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return IRQ_HANDLED;
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}
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/* read 64-bit timer counter */
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static cycle_t sirfsoc_timer_read(struct clocksource *cs)
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{
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u64 cycles;
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writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
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BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
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cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
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cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
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return cycles;
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}
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static int sirfsoc_timer_set_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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int cpu = smp_processor_id();
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/* disable timer first, then modify the related registers */
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sirfsoc_timer_count_disable(cpu);
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
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4 * cpu);
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writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
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4 * cpu);
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/* enable the tick */
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sirfsoc_timer_count_enable(cpu);
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return 0;
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}
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static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *ce)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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/* enable in set_next_event */
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break;
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default:
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break;
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}
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sirfsoc_timer_count_disable(smp_processor_id());
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}
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static void sirfsoc_clocksource_suspend(struct clocksource *cs)
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{
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int i;
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for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
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sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
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}
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static void sirfsoc_clocksource_resume(struct clocksource *cs)
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{
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int i;
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for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
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writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
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writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
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sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
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writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
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sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
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writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
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BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
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}
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static struct clock_event_device __percpu *sirfsoc_clockevent;
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static struct clocksource sirfsoc_clocksource = {
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.name = "sirfsoc_clocksource",
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.rating = 200,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.read = sirfsoc_timer_read,
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.suspend = sirfsoc_clocksource_suspend,
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.resume = sirfsoc_clocksource_resume,
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};
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static struct irqaction sirfsoc_timer_irq = {
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.name = "sirfsoc_timer0",
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.flags = IRQF_TIMER | IRQF_NOBALANCING,
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.handler = sirfsoc_timer_interrupt,
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};
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static struct irqaction sirfsoc_timer1_irq = {
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.name = "sirfsoc_timer1",
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.flags = IRQF_TIMER | IRQF_NOBALANCING,
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.handler = sirfsoc_timer_interrupt,
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};
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static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
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{
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int cpu = smp_processor_id();
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struct irqaction *action;
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if (cpu == 0)
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action = &sirfsoc_timer_irq;
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else
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action = &sirfsoc_timer1_irq;
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ce->irq = action->irq;
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ce->name = "local_timer";
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ce->features = CLOCK_EVT_FEAT_ONESHOT;
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ce->rating = 200;
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ce->set_mode = sirfsoc_timer_set_mode;
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ce->set_next_event = sirfsoc_timer_set_next_event;
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clockevents_calc_mult_shift(ce, marco_timer_rate, 60);
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ce->max_delta_ns = clockevent_delta2ns(-2, ce);
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ce->min_delta_ns = clockevent_delta2ns(2, ce);
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ce->cpumask = cpumask_of(cpu);
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action->dev_id = ce;
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BUG_ON(setup_irq(ce->irq, action));
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irq_force_affinity(action->irq, cpumask_of(cpu));
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clockevents_register_device(ce);
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return 0;
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}
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static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
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{
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int cpu = smp_processor_id();
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sirfsoc_timer_count_disable(1);
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if (cpu == 0)
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remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
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else
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remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
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}
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static int sirfsoc_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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/*
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* Grab cpu pointer in each case to avoid spurious
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* preemptible warnings
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*/
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_STARTING:
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sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
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break;
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case CPU_DYING:
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sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block sirfsoc_cpu_nb = {
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.notifier_call = sirfsoc_cpu_notify,
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};
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static void __init sirfsoc_clockevent_init(void)
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{
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sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
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BUG_ON(!sirfsoc_clockevent);
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BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));
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/* Immediately configure the timer on the boot CPU */
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sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
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}
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/* initialize the kernel jiffy timer source */
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static void __init sirfsoc_marco_timer_init(struct device_node *np)
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{
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u32 timer_div;
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struct clk *clk;
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clk = of_clk_get(np, 0);
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BUG_ON(IS_ERR(clk));
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BUG_ON(clk_prepare_enable(clk));
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marco_timer_rate = clk_get_rate(clk);
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/* timer dividers: 0, not divided */
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
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/* Initialize timer counters to 0 */
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
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writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
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BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
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/* Clear all interrupts */
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writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
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BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, marco_timer_rate));
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sirfsoc_clockevent_init();
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}
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static void __init sirfsoc_of_timer_init(struct device_node *np)
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{
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sirfsoc_timer_base = of_iomap(np, 0);
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if (!sirfsoc_timer_base)
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panic("unable to map timer cpu registers\n");
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sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
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if (!sirfsoc_timer_irq.irq)
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panic("No irq passed for timer0 via DT\n");
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sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
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if (!sirfsoc_timer1_irq.irq)
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panic("No irq passed for timer1 via DT\n");
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sirfsoc_marco_timer_init(np);
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}
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CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );
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