7afd7f6aa2
An iommu domain could be allocated and mapped before it's attached to any device. This requires that in scalable mode, when the domain is allocated, the format (FL or SL) of the page table must be determined. In order to achieve this, the platform should support consistent SL or FL capabilities on all IOMMU's. This adds a check for this and aborts IOMMU probing if it doesn't meet this requirement. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Link: https://lore.kernel.org/r/20210926114535.923263-1-baolu.lu@linux.intel.com Link: https://lore.kernel.org/r/20211014053839.727419-5-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
219 lines
8.1 KiB
C
219 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* cap_audit.c - audit iommu capabilities for boot time and hot plug
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*
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* Copyright (C) 2021 Intel Corporation
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*
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* Author: Kyung Min Park <kyung.min.park@intel.com>
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* Lu Baolu <baolu.lu@linux.intel.com>
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*/
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#define pr_fmt(fmt) "DMAR: " fmt
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#include <linux/intel-iommu.h>
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#include "cap_audit.h"
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static u64 intel_iommu_cap_sanity;
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static u64 intel_iommu_ecap_sanity;
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static inline void check_irq_capabilities(struct intel_iommu *a,
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struct intel_iommu *b)
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{
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CHECK_FEATURE_MISMATCH(a, b, cap, pi_support, CAP_PI_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, eim_support, ECAP_EIM_MASK);
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}
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static inline void check_dmar_capabilities(struct intel_iommu *a,
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struct intel_iommu *b)
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{
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MINIMAL_FEATURE_IOMMU(b, cap, CAP_MAMV_MASK);
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MINIMAL_FEATURE_IOMMU(b, cap, CAP_NFR_MASK);
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MINIMAL_FEATURE_IOMMU(b, cap, CAP_SLLPS_MASK);
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MINIMAL_FEATURE_IOMMU(b, cap, CAP_FRO_MASK);
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MINIMAL_FEATURE_IOMMU(b, cap, CAP_MGAW_MASK);
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MINIMAL_FEATURE_IOMMU(b, cap, CAP_SAGAW_MASK);
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MINIMAL_FEATURE_IOMMU(b, cap, CAP_NDOMS_MASK);
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MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_PSS_MASK);
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MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_MHMV_MASK);
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MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_IRO_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, 5lp_support, CAP_FL5LP_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, fl1gp_support, CAP_FL1GP_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, read_drain, CAP_RD_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, write_drain, CAP_WD_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, pgsel_inv, CAP_PSI_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, zlr, CAP_ZLR_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, caching_mode, CAP_CM_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, phmr, CAP_PHMR_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, plmr, CAP_PLMR_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, rwbf, CAP_RWBF_MASK);
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CHECK_FEATURE_MISMATCH(a, b, cap, afl, CAP_AFL_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, rps, ECAP_RPS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, smpwc, ECAP_SMPWC_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, flts, ECAP_FLTS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, slts, ECAP_SLTS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, nwfs, ECAP_NWFS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, slads, ECAP_SLADS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, vcs, ECAP_VCS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, smts, ECAP_SMTS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, pds, ECAP_PDS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, dit, ECAP_DIT_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, pasid, ECAP_PASID_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, eafs, ECAP_EAFS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, srs, ECAP_SRS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, ers, ECAP_ERS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, prs, ECAP_PRS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, nest, ECAP_NEST_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, mts, ECAP_MTS_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, sc_support, ECAP_SC_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, pass_through, ECAP_PT_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, dev_iotlb_support, ECAP_DT_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, qis, ECAP_QI_MASK);
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CHECK_FEATURE_MISMATCH(a, b, ecap, coherent, ECAP_C_MASK);
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}
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static int cap_audit_hotplug(struct intel_iommu *iommu, enum cap_audit_type type)
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{
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bool mismatch = false;
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u64 old_cap = intel_iommu_cap_sanity;
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u64 old_ecap = intel_iommu_ecap_sanity;
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if (type == CAP_AUDIT_HOTPLUG_IRQR) {
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, pi_support, CAP_PI_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, eim_support, ECAP_EIM_MASK);
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goto out;
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}
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, 5lp_support, CAP_FL5LP_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl1gp_support, CAP_FL1GP_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, read_drain, CAP_RD_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, write_drain, CAP_WD_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, pgsel_inv, CAP_PSI_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, zlr, CAP_ZLR_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, caching_mode, CAP_CM_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, phmr, CAP_PHMR_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, plmr, CAP_PLMR_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, rwbf, CAP_RWBF_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, afl, CAP_AFL_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, rps, ECAP_RPS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, smpwc, ECAP_SMPWC_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, flts, ECAP_FLTS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, slts, ECAP_SLTS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, nwfs, ECAP_NWFS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, slads, ECAP_SLADS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, vcs, ECAP_VCS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, smts, ECAP_SMTS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pds, ECAP_PDS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, dit, ECAP_DIT_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pasid, ECAP_PASID_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, eafs, ECAP_EAFS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, srs, ECAP_SRS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, ers, ECAP_ERS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, prs, ECAP_PRS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, nest, ECAP_NEST_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, mts, ECAP_MTS_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, sc_support, ECAP_SC_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pass_through, ECAP_PT_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, dev_iotlb_support, ECAP_DT_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, qis, ECAP_QI_MASK);
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CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, coherent, ECAP_C_MASK);
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/* Abort hot plug if the hot plug iommu feature is smaller than global */
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MINIMAL_FEATURE_HOTPLUG(iommu, cap, max_amask_val, CAP_MAMV_MASK, mismatch);
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MINIMAL_FEATURE_HOTPLUG(iommu, cap, num_fault_regs, CAP_NFR_MASK, mismatch);
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MINIMAL_FEATURE_HOTPLUG(iommu, cap, super_page_val, CAP_SLLPS_MASK, mismatch);
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MINIMAL_FEATURE_HOTPLUG(iommu, cap, fault_reg_offset, CAP_FRO_MASK, mismatch);
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MINIMAL_FEATURE_HOTPLUG(iommu, cap, mgaw, CAP_MGAW_MASK, mismatch);
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MINIMAL_FEATURE_HOTPLUG(iommu, cap, sagaw, CAP_SAGAW_MASK, mismatch);
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MINIMAL_FEATURE_HOTPLUG(iommu, cap, ndoms, CAP_NDOMS_MASK, mismatch);
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MINIMAL_FEATURE_HOTPLUG(iommu, ecap, pss, ECAP_PSS_MASK, mismatch);
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MINIMAL_FEATURE_HOTPLUG(iommu, ecap, max_handle_mask, ECAP_MHMV_MASK, mismatch);
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MINIMAL_FEATURE_HOTPLUG(iommu, ecap, iotlb_offset, ECAP_IRO_MASK, mismatch);
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out:
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if (mismatch) {
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intel_iommu_cap_sanity = old_cap;
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intel_iommu_ecap_sanity = old_ecap;
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return -EFAULT;
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}
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return 0;
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}
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static int cap_audit_static(struct intel_iommu *iommu, enum cap_audit_type type)
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{
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struct dmar_drhd_unit *d;
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struct intel_iommu *i;
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rcu_read_lock();
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if (list_empty(&dmar_drhd_units))
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goto out;
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for_each_active_iommu(i, d) {
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if (!iommu) {
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intel_iommu_ecap_sanity = i->ecap;
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intel_iommu_cap_sanity = i->cap;
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iommu = i;
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continue;
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}
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if (type == CAP_AUDIT_STATIC_DMAR)
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check_dmar_capabilities(iommu, i);
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else
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check_irq_capabilities(iommu, i);
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}
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/*
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* If the system is sane to support scalable mode, either SL or FL
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* should be sane.
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*/
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if (intel_cap_smts_sanity() &&
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!intel_cap_flts_sanity() && !intel_cap_slts_sanity())
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return -EOPNOTSUPP;
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out:
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rcu_read_unlock();
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return 0;
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}
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int intel_cap_audit(enum cap_audit_type type, struct intel_iommu *iommu)
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{
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switch (type) {
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case CAP_AUDIT_STATIC_DMAR:
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case CAP_AUDIT_STATIC_IRQR:
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return cap_audit_static(iommu, type);
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case CAP_AUDIT_HOTPLUG_DMAR:
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case CAP_AUDIT_HOTPLUG_IRQR:
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return cap_audit_hotplug(iommu, type);
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default:
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break;
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}
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return -EFAULT;
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}
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bool intel_cap_smts_sanity(void)
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{
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return ecap_smts(intel_iommu_ecap_sanity);
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}
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bool intel_cap_pasid_sanity(void)
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{
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return ecap_pasid(intel_iommu_ecap_sanity);
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}
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bool intel_cap_nest_sanity(void)
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{
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return ecap_nest(intel_iommu_ecap_sanity);
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}
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bool intel_cap_flts_sanity(void)
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{
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return ecap_flts(intel_iommu_ecap_sanity);
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}
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bool intel_cap_slts_sanity(void)
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{
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return ecap_slts(intel_iommu_ecap_sanity);
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}
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