9ce5884e51
PSR always had a requirement to only be enabled if there is active
planes but not following that never caused any issues.
But that changes in Alderlake-P, leaving PSR enabled without
active planes causes transcoder/port underruns.
Similar behavior was fixed during the pipe disable sequence by
commit 84030adb9e ("drm/i915/display: Disable audio, DRRS and PSR before planes").
intel_dp_compute_psr_vsc_sdp() had to move from
intel_psr_enable_locked() to intel_psr_compute_config() because we
need to be able to disable/enable PSR from atomic states without
connector and encoder state.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210922215242.66683-3-jose.souza@intel.com
57 lines
2.1 KiB
C
57 lines
2.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_PSR_H__
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#define __INTEL_PSR_H__
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#include "intel_frontbuffer.h"
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struct drm_connector;
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struct drm_connector_state;
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struct drm_i915_private;
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struct intel_crtc_state;
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struct intel_dp;
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struct intel_crtc;
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struct intel_atomic_state;
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struct intel_plane_state;
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struct intel_plane;
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struct intel_encoder;
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void intel_psr_init_dpcd(struct intel_dp *intel_dp);
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void intel_psr_pre_plane_update(const struct intel_atomic_state *state);
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void intel_psr_post_plane_update(const struct intel_atomic_state *state);
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void intel_psr_disable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *old_crtc_state);
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int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
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void intel_psr_invalidate(struct drm_i915_private *dev_priv,
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unsigned frontbuffer_bits,
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enum fb_op_origin origin);
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void intel_psr_flush(struct drm_i915_private *dev_priv,
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unsigned frontbuffer_bits,
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enum fb_op_origin origin);
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void intel_psr_init(struct intel_dp *intel_dp);
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void intel_psr_compute_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state);
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void intel_psr_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config);
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void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
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void intel_psr_short_pulse(struct intel_dp *intel_dp);
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void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
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bool intel_psr_enabled(struct intel_dp *intel_dp);
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int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
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void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state,
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int color_plane);
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void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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void intel_psr_pause(struct intel_dp *intel_dp);
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void intel_psr_resume(struct intel_dp *intel_dp);
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#endif /* __INTEL_PSR_H__ */
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