forked from Minki/linux
9a2ac2dcdc
The majority of the code in this driver is licensed under the GPL v2, so relicense the rest under GPL v2 as well for consistency. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
958 lines
24 KiB
C
958 lines
24 KiB
C
/*
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* Copyright (C) 2013 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/host1x.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_panel.h>
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#include <video/mipi_display.h>
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#include "dc.h"
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#include "drm.h"
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#include "dsi.h"
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#include "mipi-phy.h"
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#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
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#define DSI_HOST_FIFO_DEPTH 64
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struct tegra_dsi {
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struct host1x_client client;
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struct tegra_output output;
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struct device *dev;
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void __iomem *regs;
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struct reset_control *rst;
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struct clk *clk_parent;
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struct clk *clk_lp;
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struct clk *clk;
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struct drm_info_list *debugfs_files;
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struct drm_minor *minor;
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struct dentry *debugfs;
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enum mipi_dsi_pixel_format format;
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unsigned int lanes;
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struct tegra_mipi_device *mipi;
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struct mipi_dsi_host host;
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};
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static inline struct tegra_dsi *
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host1x_client_to_dsi(struct host1x_client *client)
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{
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return container_of(client, struct tegra_dsi, client);
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}
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static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
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{
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return container_of(host, struct tegra_dsi, host);
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}
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static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
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{
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return container_of(output, struct tegra_dsi, output);
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}
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static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
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unsigned long reg)
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{
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return readl(dsi->regs + (reg << 2));
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}
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static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
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unsigned long reg)
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{
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writel(value, dsi->regs + (reg << 2));
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}
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static int tegra_dsi_show_regs(struct seq_file *s, void *data)
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{
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struct drm_info_node *node = s->private;
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struct tegra_dsi *dsi = node->info_ent->data;
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#define DUMP_REG(name) \
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seq_printf(s, "%-32s %#05x %08lx\n", #name, name, \
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tegra_dsi_readl(dsi, name))
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DUMP_REG(DSI_INCR_SYNCPT);
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DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
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DUMP_REG(DSI_INCR_SYNCPT_ERROR);
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DUMP_REG(DSI_CTXSW);
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DUMP_REG(DSI_RD_DATA);
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DUMP_REG(DSI_WR_DATA);
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DUMP_REG(DSI_POWER_CONTROL);
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DUMP_REG(DSI_INT_ENABLE);
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DUMP_REG(DSI_INT_STATUS);
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DUMP_REG(DSI_INT_MASK);
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DUMP_REG(DSI_HOST_CONTROL);
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DUMP_REG(DSI_CONTROL);
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DUMP_REG(DSI_SOL_DELAY);
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DUMP_REG(DSI_MAX_THRESHOLD);
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DUMP_REG(DSI_TRIGGER);
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DUMP_REG(DSI_TX_CRC);
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DUMP_REG(DSI_STATUS);
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DUMP_REG(DSI_INIT_SEQ_CONTROL);
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DUMP_REG(DSI_INIT_SEQ_DATA_0);
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DUMP_REG(DSI_INIT_SEQ_DATA_1);
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DUMP_REG(DSI_INIT_SEQ_DATA_2);
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DUMP_REG(DSI_INIT_SEQ_DATA_3);
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DUMP_REG(DSI_INIT_SEQ_DATA_4);
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DUMP_REG(DSI_INIT_SEQ_DATA_5);
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DUMP_REG(DSI_INIT_SEQ_DATA_6);
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DUMP_REG(DSI_INIT_SEQ_DATA_7);
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DUMP_REG(DSI_PKT_SEQ_0_LO);
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DUMP_REG(DSI_PKT_SEQ_0_HI);
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DUMP_REG(DSI_PKT_SEQ_1_LO);
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DUMP_REG(DSI_PKT_SEQ_1_HI);
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DUMP_REG(DSI_PKT_SEQ_2_LO);
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DUMP_REG(DSI_PKT_SEQ_2_HI);
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DUMP_REG(DSI_PKT_SEQ_3_LO);
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DUMP_REG(DSI_PKT_SEQ_3_HI);
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DUMP_REG(DSI_PKT_SEQ_4_LO);
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DUMP_REG(DSI_PKT_SEQ_4_HI);
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DUMP_REG(DSI_PKT_SEQ_5_LO);
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DUMP_REG(DSI_PKT_SEQ_5_HI);
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DUMP_REG(DSI_DCS_CMDS);
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DUMP_REG(DSI_PKT_LEN_0_1);
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DUMP_REG(DSI_PKT_LEN_2_3);
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DUMP_REG(DSI_PKT_LEN_4_5);
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DUMP_REG(DSI_PKT_LEN_6_7);
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DUMP_REG(DSI_PHY_TIMING_0);
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DUMP_REG(DSI_PHY_TIMING_1);
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DUMP_REG(DSI_PHY_TIMING_2);
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DUMP_REG(DSI_BTA_TIMING);
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DUMP_REG(DSI_TIMEOUT_0);
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DUMP_REG(DSI_TIMEOUT_1);
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DUMP_REG(DSI_TO_TALLY);
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DUMP_REG(DSI_PAD_CONTROL_0);
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DUMP_REG(DSI_PAD_CONTROL_CD);
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DUMP_REG(DSI_PAD_CD_STATUS);
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DUMP_REG(DSI_VIDEO_MODE_CONTROL);
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DUMP_REG(DSI_PAD_CONTROL_1);
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DUMP_REG(DSI_PAD_CONTROL_2);
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DUMP_REG(DSI_PAD_CONTROL_3);
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DUMP_REG(DSI_PAD_CONTROL_4);
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DUMP_REG(DSI_GANGED_MODE_CONTROL);
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DUMP_REG(DSI_GANGED_MODE_START);
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DUMP_REG(DSI_GANGED_MODE_SIZE);
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DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
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DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
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DUMP_REG(DSI_INIT_SEQ_DATA_8);
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DUMP_REG(DSI_INIT_SEQ_DATA_9);
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DUMP_REG(DSI_INIT_SEQ_DATA_10);
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DUMP_REG(DSI_INIT_SEQ_DATA_11);
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DUMP_REG(DSI_INIT_SEQ_DATA_12);
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DUMP_REG(DSI_INIT_SEQ_DATA_13);
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DUMP_REG(DSI_INIT_SEQ_DATA_14);
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DUMP_REG(DSI_INIT_SEQ_DATA_15);
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#undef DUMP_REG
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return 0;
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}
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static struct drm_info_list debugfs_files[] = {
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{ "regs", tegra_dsi_show_regs, 0, NULL },
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};
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static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
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struct drm_minor *minor)
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{
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const char *name = dev_name(dsi->dev);
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unsigned int i;
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int err;
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dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
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if (!dsi->debugfs)
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return -ENOMEM;
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dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
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GFP_KERNEL);
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if (!dsi->debugfs_files) {
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err = -ENOMEM;
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goto remove;
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}
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for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
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dsi->debugfs_files[i].data = dsi;
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err = drm_debugfs_create_files(dsi->debugfs_files,
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ARRAY_SIZE(debugfs_files),
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dsi->debugfs, minor);
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if (err < 0)
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goto free;
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dsi->minor = minor;
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return 0;
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free:
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kfree(dsi->debugfs_files);
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dsi->debugfs_files = NULL;
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remove:
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debugfs_remove(dsi->debugfs);
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dsi->debugfs = NULL;
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return err;
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}
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static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
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{
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drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
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dsi->minor);
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dsi->minor = NULL;
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kfree(dsi->debugfs_files);
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dsi->debugfs_files = NULL;
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debugfs_remove(dsi->debugfs);
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dsi->debugfs = NULL;
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return 0;
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}
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#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
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#define PKT_LEN0(len) (((len) & 0x07) << 0)
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#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
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#define PKT_LEN1(len) (((len) & 0x07) << 10)
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#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
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#define PKT_LEN2(len) (((len) & 0x07) << 20)
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#define PKT_LP (1 << 30)
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#define NUM_PKT_SEQ 12
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/* non-burst mode with sync-end */
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static const u32 pkt_seq_vnb_syne[NUM_PKT_SEQ] = {
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[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
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PKT_LP,
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[ 1] = 0,
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[ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
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PKT_LP,
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[ 3] = 0,
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[ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
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PKT_LP,
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[ 5] = 0,
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[ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
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[ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
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PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
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PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
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[ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
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PKT_LP,
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[ 9] = 0,
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[10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
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PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
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PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
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[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
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PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
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PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
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};
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static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
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{
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struct mipi_dphy_timing timing;
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unsigned long value, period;
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long rate;
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int err;
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rate = clk_get_rate(dsi->clk);
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if (rate < 0)
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return rate;
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period = DIV_ROUND_CLOSEST(1000000000UL, rate * 2);
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err = mipi_dphy_timing_get_default(&timing, period);
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if (err < 0)
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return err;
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err = mipi_dphy_timing_validate(&timing, period);
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if (err < 0) {
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dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
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return err;
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}
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/*
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* The D-PHY timing fields below are expressed in byte-clock cycles,
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* so multiply the period by 8.
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*/
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period *= 8;
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value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
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DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
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DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
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DSI_TIMING_FIELD(timing.hsprepare, period, 1);
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tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
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value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
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DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
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DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
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DSI_TIMING_FIELD(timing.lpx, period, 1);
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tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
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value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
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DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
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DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
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tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
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value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
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DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
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DSI_TIMING_FIELD(timing.tago, period, 1);
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tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
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return 0;
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}
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static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
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unsigned int *mulp, unsigned int *divp)
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{
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switch (format) {
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case MIPI_DSI_FMT_RGB666_PACKED:
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case MIPI_DSI_FMT_RGB888:
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*mulp = 3;
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*divp = 1;
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break;
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case MIPI_DSI_FMT_RGB565:
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*mulp = 2;
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*divp = 1;
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break;
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case MIPI_DSI_FMT_RGB666:
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*mulp = 9;
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*divp = 4;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int tegra_output_dsi_enable(struct tegra_output *output)
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{
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struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
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struct drm_display_mode *mode = &dc->base.mode;
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unsigned int hact, hsw, hbp, hfp, i, mul, div;
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struct tegra_dsi *dsi = to_dsi(output);
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/* FIXME: don't hardcode this */
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const u32 *pkt_seq = pkt_seq_vnb_syne;
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unsigned long value;
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int err;
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err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
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if (err < 0)
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return err;
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err = clk_enable(dsi->clk);
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if (err < 0)
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return err;
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reset_control_deassert(dsi->rst);
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value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(dsi->format) |
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DSI_CONTROL_LANES(dsi->lanes - 1) |
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DSI_CONTROL_SOURCE(dc->pipe);
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tegra_dsi_writel(dsi, value, DSI_CONTROL);
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tegra_dsi_writel(dsi, DSI_VIDEO_FIFO_DEPTH, DSI_MAX_THRESHOLD);
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value = DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS |
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DSI_HOST_CONTROL_ECC;
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tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
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value = tegra_dsi_readl(dsi, DSI_CONTROL);
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value |= DSI_CONTROL_HS_CLK_CTRL;
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value &= ~DSI_CONTROL_TX_TRIG(3);
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value &= ~DSI_CONTROL_DCS_ENABLE;
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value |= DSI_CONTROL_VIDEO_ENABLE;
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value &= ~DSI_CONTROL_HOST_ENABLE;
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tegra_dsi_writel(dsi, value, DSI_CONTROL);
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err = tegra_dsi_set_phy_timing(dsi);
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if (err < 0)
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return err;
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for (i = 0; i < NUM_PKT_SEQ; i++)
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tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
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/* horizontal active pixels */
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hact = mode->hdisplay * mul / div;
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/* horizontal sync width */
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hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
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hsw -= 10;
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/* horizontal back porch */
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hbp = (mode->htotal - mode->hsync_end) * mul / div;
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hbp -= 14;
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/* horizontal front porch */
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hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
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hfp -= 8;
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tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
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tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
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tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
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tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
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/* set SOL delay */
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tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
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/* enable display controller */
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value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
|
value |= DSI_ENABLE;
|
|
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
|
|
|
value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
|
|
value &= ~DISP_CTRL_MODE_MASK;
|
|
value |= DISP_CTRL_MODE_C_DISPLAY;
|
|
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
|
|
|
|
value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
|
|
value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
|
|
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
|
|
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
|
|
|
|
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
|
|
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
|
|
|
|
/* enable DSI controller */
|
|
value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
|
|
value |= DSI_POWER_CONTROL_ENABLE;
|
|
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_output_dsi_disable(struct tegra_output *output)
|
|
{
|
|
struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
|
|
struct tegra_dsi *dsi = to_dsi(output);
|
|
unsigned long value;
|
|
|
|
/* disable DSI controller */
|
|
value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
|
|
value &= DSI_POWER_CONTROL_ENABLE;
|
|
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
|
|
|
|
/*
|
|
* The following accesses registers of the display controller, so make
|
|
* sure it's only executed when the output is attached to one.
|
|
*/
|
|
if (dc) {
|
|
value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
|
|
value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
|
|
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
|
|
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
|
|
|
|
value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
|
|
value &= ~DISP_CTRL_MODE_MASK;
|
|
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
|
|
|
|
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
|
value &= ~DSI_ENABLE;
|
|
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
|
|
|
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
|
|
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
|
|
}
|
|
|
|
clk_disable(dsi->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_output_dsi_setup_clock(struct tegra_output *output,
|
|
struct clk *clk, unsigned long pclk)
|
|
{
|
|
struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
|
|
struct drm_display_mode *mode = &dc->base.mode;
|
|
unsigned int timeout, mul, div, vrefresh;
|
|
struct tegra_dsi *dsi = to_dsi(output);
|
|
unsigned long bclk, plld, value;
|
|
struct clk *base;
|
|
int err;
|
|
|
|
err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
vrefresh = drm_mode_vrefresh(mode);
|
|
|
|
pclk = mode->htotal * mode->vtotal * vrefresh;
|
|
bclk = (pclk * mul) / (div * dsi->lanes);
|
|
plld = DIV_ROUND_UP(bclk * 8, 1000000);
|
|
pclk = (plld * 1000000) / 2;
|
|
|
|
err = clk_set_parent(clk, dsi->clk_parent);
|
|
if (err < 0) {
|
|
dev_err(dsi->dev, "failed to set parent clock: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
base = clk_get_parent(dsi->clk_parent);
|
|
|
|
/*
|
|
* This assumes that the parent clock is pll_d_out0 or pll_d2_out
|
|
* respectively, each of which divides the base pll_d by 2.
|
|
*/
|
|
err = clk_set_rate(base, pclk * 2);
|
|
if (err < 0) {
|
|
dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
|
|
pclk * 2);
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* XXX: Move the below somewhere else so that we don't need to have
|
|
* access to the vrefresh in this function?
|
|
*/
|
|
|
|
/* one frame high-speed transmission timeout */
|
|
timeout = (bclk / vrefresh) / 512;
|
|
value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
|
|
tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
|
|
|
|
/* 2 ms peripheral timeout for panel */
|
|
timeout = 2 * bclk / 512 * 1000;
|
|
value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
|
|
tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
|
|
|
|
value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
|
|
tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_output_dsi_check_mode(struct tegra_output *output,
|
|
struct drm_display_mode *mode,
|
|
enum drm_mode_status *status)
|
|
{
|
|
/*
|
|
* FIXME: For now, always assume that the mode is okay.
|
|
*/
|
|
|
|
*status = MODE_OK;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct tegra_output_ops dsi_ops = {
|
|
.enable = tegra_output_dsi_enable,
|
|
.disable = tegra_output_dsi_disable,
|
|
.setup_clock = tegra_output_dsi_setup_clock,
|
|
.check_mode = tegra_output_dsi_check_mode,
|
|
};
|
|
|
|
static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
|
|
{
|
|
unsigned long value;
|
|
|
|
value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
|
|
tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
|
|
{
|
|
unsigned long value;
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
|
|
|
|
/* start calibration */
|
|
tegra_dsi_pad_enable(dsi);
|
|
|
|
value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
|
|
DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
|
|
DSI_PAD_OUT_CLK(0x0);
|
|
tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
|
|
|
|
return tegra_mipi_calibrate(dsi->mipi);
|
|
}
|
|
|
|
static int tegra_dsi_init(struct host1x_client *client)
|
|
{
|
|
struct tegra_drm *tegra = dev_get_drvdata(client->parent);
|
|
struct tegra_dsi *dsi = host1x_client_to_dsi(client);
|
|
unsigned long value, i;
|
|
int err;
|
|
|
|
dsi->output.type = TEGRA_OUTPUT_DSI;
|
|
dsi->output.dev = client->dev;
|
|
dsi->output.ops = &dsi_ops;
|
|
|
|
err = tegra_output_init(tegra->drm, &dsi->output);
|
|
if (err < 0) {
|
|
dev_err(client->dev, "output setup failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
|
|
err = tegra_dsi_debugfs_init(dsi, tegra->drm->primary);
|
|
if (err < 0)
|
|
dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
|
|
}
|
|
|
|
/*
|
|
* enable high-speed mode, checksum generation, ECC generation and
|
|
* disable raw mode
|
|
*/
|
|
value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
|
|
value |= DSI_HOST_CONTROL_ECC | DSI_HOST_CONTROL_CS |
|
|
DSI_HOST_CONTROL_HS;
|
|
value &= ~DSI_HOST_CONTROL_RAW;
|
|
tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
|
|
tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
|
|
tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
|
|
}
|
|
|
|
for (i = 0; i < 12; i++)
|
|
tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
|
|
|
|
err = tegra_dsi_pad_calibrate(dsi);
|
|
if (err < 0) {
|
|
dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
tegra_dsi_writel(dsi, DSI_POWER_CONTROL_ENABLE, DSI_POWER_CONTROL);
|
|
usleep_range(300, 1000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dsi_exit(struct host1x_client *client)
|
|
{
|
|
struct tegra_dsi *dsi = host1x_client_to_dsi(client);
|
|
int err;
|
|
|
|
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
|
|
err = tegra_dsi_debugfs_exit(dsi);
|
|
if (err < 0)
|
|
dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
|
|
}
|
|
|
|
err = tegra_output_disable(&dsi->output);
|
|
if (err < 0) {
|
|
dev_err(client->dev, "output failed to disable: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
err = tegra_output_exit(&dsi->output);
|
|
if (err < 0) {
|
|
dev_err(client->dev, "output cleanup failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct host1x_client_ops dsi_client_ops = {
|
|
.init = tegra_dsi_init,
|
|
.exit = tegra_dsi_exit,
|
|
};
|
|
|
|
static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
|
|
{
|
|
struct clk *parent;
|
|
int err;
|
|
|
|
parent = clk_get_parent(dsi->clk);
|
|
if (!parent)
|
|
return -EINVAL;
|
|
|
|
err = clk_set_parent(parent, dsi->clk_parent);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_dsi_initialize(struct tegra_dsi *dsi)
|
|
{
|
|
unsigned int i;
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_POWER_CONTROL);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_INT_ENABLE);
|
|
tegra_dsi_writel(dsi, 0, DSI_INT_STATUS);
|
|
tegra_dsi_writel(dsi, 0, DSI_INT_MASK);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_HOST_CONTROL);
|
|
tegra_dsi_writel(dsi, 0, DSI_CONTROL);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
|
|
tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
|
|
tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
|
|
}
|
|
|
|
for (i = 0; i < 12; i++)
|
|
tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
|
|
|
|
for (i = 0; i < 4; i++)
|
|
tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1 + i);
|
|
|
|
tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_0);
|
|
tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_1);
|
|
tegra_dsi_writel(dsi, 0x000000ff, DSI_PHY_TIMING_2);
|
|
tegra_dsi_writel(dsi, 0x00000000, DSI_BTA_TIMING);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_0);
|
|
tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_1);
|
|
tegra_dsi_writel(dsi, 0, DSI_TO_TALLY);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_CD);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CD_STATUS);
|
|
tegra_dsi_writel(dsi, 0, DSI_VIDEO_MODE_CONTROL);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
|
|
tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
|
|
|
|
tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
|
|
tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
|
|
tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
|
|
}
|
|
|
|
static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
|
|
struct mipi_dsi_device *device)
|
|
{
|
|
struct tegra_dsi *dsi = host_to_tegra(host);
|
|
struct tegra_output *output = &dsi->output;
|
|
|
|
dsi->format = device->format;
|
|
dsi->lanes = device->lanes;
|
|
|
|
output->panel = of_drm_find_panel(device->dev.of_node);
|
|
if (output->panel) {
|
|
if (output->connector.dev)
|
|
drm_helper_hpd_irq_event(output->connector.dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
|
|
struct mipi_dsi_device *device)
|
|
{
|
|
struct tegra_dsi *dsi = host_to_tegra(host);
|
|
struct tegra_output *output = &dsi->output;
|
|
|
|
if (output->panel && &device->dev == output->panel->dev) {
|
|
if (output->connector.dev)
|
|
drm_helper_hpd_irq_event(output->connector.dev);
|
|
|
|
output->panel = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
|
|
.attach = tegra_dsi_host_attach,
|
|
.detach = tegra_dsi_host_detach,
|
|
};
|
|
|
|
static int tegra_dsi_probe(struct platform_device *pdev)
|
|
{
|
|
struct tegra_dsi *dsi;
|
|
struct resource *regs;
|
|
int err;
|
|
|
|
dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
|
|
if (!dsi)
|
|
return -ENOMEM;
|
|
|
|
dsi->output.dev = dsi->dev = &pdev->dev;
|
|
|
|
err = tegra_output_probe(&dsi->output);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/*
|
|
* Assume these values by default. When a DSI peripheral driver
|
|
* attaches to the DSI host, the parameters will be taken from
|
|
* the attached device.
|
|
*/
|
|
dsi->format = MIPI_DSI_FMT_RGB888;
|
|
dsi->lanes = 4;
|
|
|
|
dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
|
|
if (IS_ERR(dsi->rst))
|
|
return PTR_ERR(dsi->rst);
|
|
|
|
dsi->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(dsi->clk)) {
|
|
dev_err(&pdev->dev, "cannot get DSI clock\n");
|
|
return PTR_ERR(dsi->clk);
|
|
}
|
|
|
|
err = clk_prepare_enable(dsi->clk);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "cannot enable DSI clock\n");
|
|
return err;
|
|
}
|
|
|
|
dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
|
|
if (IS_ERR(dsi->clk_lp)) {
|
|
dev_err(&pdev->dev, "cannot get low-power clock\n");
|
|
return PTR_ERR(dsi->clk_lp);
|
|
}
|
|
|
|
err = clk_prepare_enable(dsi->clk_lp);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "cannot enable low-power clock\n");
|
|
return err;
|
|
}
|
|
|
|
dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
|
|
if (IS_ERR(dsi->clk_parent)) {
|
|
dev_err(&pdev->dev, "cannot get parent clock\n");
|
|
return PTR_ERR(dsi->clk_parent);
|
|
}
|
|
|
|
err = clk_prepare_enable(dsi->clk_parent);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "cannot enable parent clock\n");
|
|
return err;
|
|
}
|
|
|
|
err = tegra_dsi_setup_clocks(dsi);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "cannot setup clocks\n");
|
|
return err;
|
|
}
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
|
|
if (IS_ERR(dsi->regs))
|
|
return PTR_ERR(dsi->regs);
|
|
|
|
tegra_dsi_initialize(dsi);
|
|
|
|
dsi->mipi = tegra_mipi_request(&pdev->dev);
|
|
if (IS_ERR(dsi->mipi))
|
|
return PTR_ERR(dsi->mipi);
|
|
|
|
dsi->host.ops = &tegra_dsi_host_ops;
|
|
dsi->host.dev = &pdev->dev;
|
|
|
|
err = mipi_dsi_host_register(&dsi->host);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&dsi->client.list);
|
|
dsi->client.ops = &dsi_client_ops;
|
|
dsi->client.dev = &pdev->dev;
|
|
|
|
err = host1x_client_register(&dsi->client);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to register host1x client: %d\n",
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, dsi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dsi_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_dsi *dsi = platform_get_drvdata(pdev);
|
|
int err;
|
|
|
|
err = host1x_client_unregister(&dsi->client);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
mipi_dsi_host_unregister(&dsi->host);
|
|
tegra_mipi_free(dsi->mipi);
|
|
|
|
clk_disable_unprepare(dsi->clk_parent);
|
|
clk_disable_unprepare(dsi->clk_lp);
|
|
clk_disable_unprepare(dsi->clk);
|
|
|
|
err = tegra_output_remove(&dsi->output);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to remove output: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id tegra_dsi_of_match[] = {
|
|
{ .compatible = "nvidia,tegra114-dsi", },
|
|
{ },
|
|
};
|
|
|
|
struct platform_driver tegra_dsi_driver = {
|
|
.driver = {
|
|
.name = "tegra-dsi",
|
|
.of_match_table = tegra_dsi_of_match,
|
|
},
|
|
.probe = tegra_dsi_probe,
|
|
.remove = tegra_dsi_remove,
|
|
};
|