forked from Minki/linux
1c9db52534
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Tony Luck <tony.luck@intel.com> Cc: Russell King <linux@arm.linux.org.uk>
431 lines
10 KiB
C
431 lines
10 KiB
C
/*
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* Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
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*
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* Author: Tony Li <tony.li@freescale.com>
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* Jason Jin <Jason.jin@freescale.com>
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*
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* The hwirq alloc and free code reuse from sysdev/mpic_msi.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2 of the
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* License.
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*
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*/
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#include <linux/irq.h>
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#include <linux/bootmem.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/of_platform.h>
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#include <sysdev/fsl_soc.h>
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#include <asm/prom.h>
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#include <asm/hw_irq.h>
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#include <asm/ppc-pci.h>
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#include <asm/mpic.h>
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#include "fsl_msi.h"
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LIST_HEAD(msi_head);
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struct fsl_msi_feature {
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u32 fsl_pic_ip;
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u32 msiir_offset;
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};
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struct fsl_msi_cascade_data {
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struct fsl_msi *msi_data;
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int index;
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};
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static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
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{
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return in_be32(base + (reg >> 2));
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}
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/*
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* We do not need this actually. The MSIR register has been read once
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* in the cascade interrupt. So, this MSI interrupt has been acked
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*/
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static void fsl_msi_end_irq(unsigned int virq)
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{
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}
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static struct irq_chip fsl_msi_chip = {
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.irq_mask = mask_msi_irq,
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.irq_unmask = unmask_msi_irq,
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.ack = fsl_msi_end_irq,
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.name = "FSL-MSI",
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};
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static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct fsl_msi *msi_data = h->host_data;
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struct irq_chip *chip = &fsl_msi_chip;
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irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
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set_irq_chip_data(virq, msi_data);
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set_irq_chip_and_handler(virq, chip, handle_edge_irq);
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return 0;
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}
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static struct irq_host_ops fsl_msi_host_ops = {
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.map = fsl_msi_host_map,
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};
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static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
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{
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int rc;
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rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
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msi_data->irqhost->of_node);
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if (rc)
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return rc;
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rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
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if (rc < 0) {
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msi_bitmap_free(&msi_data->bitmap);
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return rc;
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}
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return 0;
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}
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static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
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{
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if (type == PCI_CAP_ID_MSIX)
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pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
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return 0;
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}
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static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct msi_desc *entry;
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struct fsl_msi *msi_data;
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list_for_each_entry(entry, &pdev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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msi_data = get_irq_data(entry->irq);
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set_irq_msi(entry->irq, NULL);
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msi_bitmap_free_hwirqs(&msi_data->bitmap,
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virq_to_hw(entry->irq), 1);
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irq_dispose_mapping(entry->irq);
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}
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return;
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}
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static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
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struct msi_msg *msg,
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struct fsl_msi *fsl_msi_data)
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{
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struct fsl_msi *msi_data = fsl_msi_data;
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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u32 base = 0;
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pci_bus_read_config_dword(hose->bus,
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PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
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msg->address_lo = msi_data->msi_addr_lo + base;
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msg->address_hi = msi_data->msi_addr_hi;
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msg->data = hwirq;
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pr_debug("%s: allocated srs: %d, ibs: %d\n",
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__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
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}
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static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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int rc, hwirq = -ENOMEM;
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unsigned int virq;
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struct msi_desc *entry;
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struct msi_msg msg;
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struct fsl_msi *msi_data;
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list_for_each_entry(entry, &pdev->msi_list, list) {
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list_for_each_entry(msi_data, &msi_head, list) {
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hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
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if (hwirq >= 0)
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break;
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}
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if (hwirq < 0) {
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rc = hwirq;
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pr_debug("%s: fail allocating msi interrupt\n",
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__func__);
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goto out_free;
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}
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virq = irq_create_mapping(msi_data->irqhost, hwirq);
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if (virq == NO_IRQ) {
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pr_debug("%s: fail mapping hwirq 0x%x\n",
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__func__, hwirq);
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msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
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rc = -ENOSPC;
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goto out_free;
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}
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set_irq_data(virq, msi_data);
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set_irq_msi(virq, entry);
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fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
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write_msi_msg(virq, &msg);
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}
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return 0;
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out_free:
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/* free by the caller of this function */
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return rc;
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}
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static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int cascade_irq;
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struct fsl_msi *msi_data;
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int msir_index = -1;
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u32 msir_value = 0;
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u32 intr_index;
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u32 have_shift = 0;
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struct fsl_msi_cascade_data *cascade_data;
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cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
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msi_data = cascade_data->msi_data;
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raw_spin_lock(&desc->lock);
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if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
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if (desc->chip->mask_ack)
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desc->chip->mask_ack(irq);
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else {
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desc->chip->mask(irq);
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desc->chip->ack(irq);
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}
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}
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if (unlikely(desc->status & IRQ_INPROGRESS))
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goto unlock;
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msir_index = cascade_data->index;
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if (msir_index >= NR_MSI_REG)
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cascade_irq = NO_IRQ;
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desc->status |= IRQ_INPROGRESS;
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switch (msi_data->feature & FSL_PIC_IP_MASK) {
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case FSL_PIC_IP_MPIC:
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msir_value = fsl_msi_read(msi_data->msi_regs,
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msir_index * 0x10);
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break;
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case FSL_PIC_IP_IPIC:
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msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
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break;
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}
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while (msir_value) {
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intr_index = ffs(msir_value) - 1;
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cascade_irq = irq_linear_revmap(msi_data->irqhost,
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msir_index * IRQS_PER_MSI_REG +
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intr_index + have_shift);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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have_shift += intr_index + 1;
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msir_value = msir_value >> (intr_index + 1);
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}
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desc->status &= ~IRQ_INPROGRESS;
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switch (msi_data->feature & FSL_PIC_IP_MASK) {
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case FSL_PIC_IP_MPIC:
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desc->chip->eoi(irq);
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break;
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case FSL_PIC_IP_IPIC:
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if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
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desc->chip->unmask(irq);
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break;
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}
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unlock:
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raw_spin_unlock(&desc->lock);
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}
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static int fsl_of_msi_remove(struct platform_device *ofdev)
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{
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struct fsl_msi *msi = ofdev->dev.platform_data;
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int virq, i;
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struct fsl_msi_cascade_data *cascade_data;
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if (msi->list.prev != NULL)
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list_del(&msi->list);
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for (i = 0; i < NR_MSI_REG; i++) {
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virq = msi->msi_virqs[i];
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if (virq != NO_IRQ) {
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cascade_data = get_irq_data(virq);
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kfree(cascade_data);
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irq_dispose_mapping(virq);
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}
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}
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if (msi->bitmap.bitmap)
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msi_bitmap_free(&msi->bitmap);
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iounmap(msi->msi_regs);
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kfree(msi);
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return 0;
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}
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static int __devinit fsl_of_msi_probe(struct platform_device *dev,
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const struct of_device_id *match)
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{
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struct fsl_msi *msi;
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struct resource res;
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int err, i, count;
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int rc;
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int virt_msir;
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const u32 *p;
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struct fsl_msi_feature *features = match->data;
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struct fsl_msi_cascade_data *cascade_data = NULL;
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int len;
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u32 offset;
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printk(KERN_DEBUG "Setting up Freescale MSI support\n");
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msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
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if (!msi) {
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dev_err(&dev->dev, "No memory for MSI structure\n");
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return -ENOMEM;
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}
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dev->dev.platform_data = msi;
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msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
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NR_MSI_IRQS, &fsl_msi_host_ops, 0);
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if (msi->irqhost == NULL) {
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dev_err(&dev->dev, "No memory for MSI irqhost\n");
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err = -ENOMEM;
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goto error_out;
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}
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/* Get the MSI reg base */
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err = of_address_to_resource(dev->dev.of_node, 0, &res);
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if (err) {
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dev_err(&dev->dev, "%s resource error!\n",
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dev->dev.of_node->full_name);
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goto error_out;
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}
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msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
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if (!msi->msi_regs) {
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dev_err(&dev->dev, "ioremap problem failed\n");
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goto error_out;
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}
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msi->feature = features->fsl_pic_ip;
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msi->irqhost->host_data = msi;
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msi->msi_addr_hi = 0x0;
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msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
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rc = fsl_msi_init_allocator(msi);
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if (rc) {
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dev_err(&dev->dev, "Error allocating MSI bitmap\n");
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goto error_out;
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}
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p = of_get_property(dev->dev.of_node, "interrupts", &count);
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if (!p) {
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dev_err(&dev->dev, "no interrupts property found on %s\n",
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dev->dev.of_node->full_name);
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err = -ENODEV;
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goto error_out;
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}
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if (count % 8 != 0) {
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dev_err(&dev->dev, "Malformed interrupts property on %s\n",
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dev->dev.of_node->full_name);
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err = -EINVAL;
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goto error_out;
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}
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offset = 0;
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p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
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if (p)
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offset = *p / IRQS_PER_MSI_REG;
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count /= sizeof(u32);
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for (i = 0; i < min(count / 2, NR_MSI_REG); i++) {
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virt_msir = irq_of_parse_and_map(dev->dev.of_node, i);
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if (virt_msir != NO_IRQ) {
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cascade_data = kzalloc(
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sizeof(struct fsl_msi_cascade_data),
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GFP_KERNEL);
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if (!cascade_data) {
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dev_err(&dev->dev,
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"No memory for MSI cascade data\n");
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err = -ENOMEM;
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goto error_out;
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}
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msi->msi_virqs[i] = virt_msir;
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cascade_data->index = i + offset;
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cascade_data->msi_data = msi;
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set_irq_data(virt_msir, (void *)cascade_data);
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set_irq_chained_handler(virt_msir, fsl_msi_cascade);
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}
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}
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list_add_tail(&msi->list, &msi_head);
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/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
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if (!ppc_md.setup_msi_irqs) {
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ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
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ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
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ppc_md.msi_check_device = fsl_msi_check_device;
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} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
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dev_err(&dev->dev, "Different MSI driver already installed!\n");
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err = -ENODEV;
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goto error_out;
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}
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return 0;
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error_out:
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fsl_of_msi_remove(dev);
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return err;
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}
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static const struct fsl_msi_feature mpic_msi_feature = {
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.fsl_pic_ip = FSL_PIC_IP_MPIC,
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.msiir_offset = 0x140,
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};
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static const struct fsl_msi_feature ipic_msi_feature = {
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.fsl_pic_ip = FSL_PIC_IP_IPIC,
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.msiir_offset = 0x38,
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};
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static const struct of_device_id fsl_of_msi_ids[] = {
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{
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.compatible = "fsl,mpic-msi",
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.data = (void *)&mpic_msi_feature,
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},
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{
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.compatible = "fsl,ipic-msi",
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.data = (void *)&ipic_msi_feature,
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},
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{}
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};
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static struct of_platform_driver fsl_of_msi_driver = {
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.driver = {
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.name = "fsl-msi",
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.owner = THIS_MODULE,
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.of_match_table = fsl_of_msi_ids,
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},
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.probe = fsl_of_msi_probe,
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.remove = fsl_of_msi_remove,
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};
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static __init int fsl_of_msi_init(void)
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{
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return of_register_platform_driver(&fsl_of_msi_driver);
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}
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subsys_initcall(fsl_of_msi_init);
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