1c5ea40c2a
[Why] When driver disabled, we driver force the YCbCr420 to RGB, which means some register will be changed, such as RDPCS_PHY_DP_MPLLB_TX_CLK_DIV changed from 1 to 0 When driver re-enabled, OS will Set Mode YCbCr420 again, which means the register RDPCS_PHY_DP_MPLLB_TX_CLK_DIV should to be 1 again, but dmub fw can’t update the register to 1 due to the mpll is not off [How] Adds an interface to disable accelerated mode bit, which allows DM to decide to call during driver disable/unload scenarios. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Yao Wang1 <Yao.Wang1@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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| acp | ||
| amdgpu | ||
| amdkfd | ||
| display | ||
| include | ||
| pm | ||