f29ad10de6
- Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data. (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1) - Add GMAC1 support and setup MUX in terms of PHY mode. - Add CPUFreq support. - Add MUX Register Definitions. - Add PWM Register Definitions. - Update clock register bitfields according to the latest spec. - Update clock related stuff. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8024/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
24 lines
680 B
C
24 lines
680 B
C
/*
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* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Loongson 1 CPUFreq platform support.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON1_CPUFREQ_H
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#define __ASM_MACH_LOONGSON1_CPUFREQ_H
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struct plat_ls1x_cpufreq {
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const char *clk_name; /* CPU clk */
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const char *osc_clk_name; /* OSC clk */
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unsigned int max_freq; /* in kHz */
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unsigned int min_freq; /* in kHz */
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};
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#endif /* __ASM_MACH_LOONGSON1_CPUFREQ_H */
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