13209a8f73
The MSCC bug fix in 'net' had to be slightly adjusted because the register accesses are done slightly differently in net-next. Signed-off-by: David S. Miller <davem@davemloft.net>
654 lines
15 KiB
C
654 lines
15 KiB
C
/*
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* B53 register access through Switch Register Access Bridge Registers
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*
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* Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/b53.h>
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#include <linux/of.h>
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#include "b53_priv.h"
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#include "b53_serdes.h"
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/* command and status register of the SRAB */
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#define B53_SRAB_CMDSTAT 0x2c
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#define B53_SRAB_CMDSTAT_RST BIT(2)
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#define B53_SRAB_CMDSTAT_WRITE BIT(1)
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#define B53_SRAB_CMDSTAT_GORDYN BIT(0)
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#define B53_SRAB_CMDSTAT_PAGE 24
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#define B53_SRAB_CMDSTAT_REG 16
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/* high order word of write data to switch registe */
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#define B53_SRAB_WD_H 0x30
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/* low order word of write data to switch registe */
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#define B53_SRAB_WD_L 0x34
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/* high order word of read data from switch register */
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#define B53_SRAB_RD_H 0x38
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/* low order word of read data from switch register */
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#define B53_SRAB_RD_L 0x3c
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/* command and status register of the SRAB */
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#define B53_SRAB_CTRLS 0x40
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#define B53_SRAB_CTRLS_HOST_INTR BIT(1)
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#define B53_SRAB_CTRLS_RCAREQ BIT(3)
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#define B53_SRAB_CTRLS_RCAGNT BIT(4)
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#define B53_SRAB_CTRLS_SW_INIT_DONE BIT(6)
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/* the register captures interrupt pulses from the switch */
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#define B53_SRAB_INTR 0x44
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#define B53_SRAB_INTR_P(x) BIT(x)
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#define B53_SRAB_SWITCH_PHY BIT(8)
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#define B53_SRAB_1588_SYNC BIT(9)
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#define B53_SRAB_IMP1_SLEEP_TIMER BIT(10)
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#define B53_SRAB_P7_SLEEP_TIMER BIT(11)
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#define B53_SRAB_IMP0_SLEEP_TIMER BIT(12)
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/* Port mux configuration registers */
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#define B53_MUX_CONFIG_P5 0x00
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#define MUX_CONFIG_SGMII 0
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#define MUX_CONFIG_MII_LITE 1
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#define MUX_CONFIG_RGMII 2
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#define MUX_CONFIG_GMII 3
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#define MUX_CONFIG_GPHY 4
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#define MUX_CONFIG_INTERNAL 5
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#define MUX_CONFIG_MASK 0x7
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#define B53_MUX_CONFIG_P4 0x04
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struct b53_srab_port_priv {
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int irq;
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bool irq_enabled;
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struct b53_device *dev;
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unsigned int num;
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phy_interface_t mode;
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};
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struct b53_srab_priv {
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void __iomem *regs;
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void __iomem *mux_config;
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struct b53_srab_port_priv port_intrs[B53_N_PORTS];
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};
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static int b53_srab_request_grant(struct b53_device *dev)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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u32 ctrls;
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int i;
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ctrls = readl(regs + B53_SRAB_CTRLS);
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ctrls |= B53_SRAB_CTRLS_RCAREQ;
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writel(ctrls, regs + B53_SRAB_CTRLS);
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for (i = 0; i < 20; i++) {
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ctrls = readl(regs + B53_SRAB_CTRLS);
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if (ctrls & B53_SRAB_CTRLS_RCAGNT)
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break;
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usleep_range(10, 100);
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}
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if (WARN_ON(i == 5))
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return -EIO;
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return 0;
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}
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static void b53_srab_release_grant(struct b53_device *dev)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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u32 ctrls;
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ctrls = readl(regs + B53_SRAB_CTRLS);
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ctrls &= ~B53_SRAB_CTRLS_RCAREQ;
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writel(ctrls, regs + B53_SRAB_CTRLS);
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}
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static int b53_srab_op(struct b53_device *dev, u8 page, u8 reg, u32 op)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int i;
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u32 cmdstat;
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/* set register address */
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cmdstat = (page << B53_SRAB_CMDSTAT_PAGE) |
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(reg << B53_SRAB_CMDSTAT_REG) |
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B53_SRAB_CMDSTAT_GORDYN |
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op;
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writel(cmdstat, regs + B53_SRAB_CMDSTAT);
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/* check if operation completed */
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for (i = 0; i < 5; ++i) {
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cmdstat = readl(regs + B53_SRAB_CMDSTAT);
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if (!(cmdstat & B53_SRAB_CMDSTAT_GORDYN))
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break;
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usleep_range(10, 100);
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}
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if (WARN_ON(i == 5))
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return -EIO;
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return 0;
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}
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static int b53_srab_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L) & 0xff;
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L) & 0xffff;
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L);
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*val += ((u64)readl(regs + B53_SRAB_RD_H) & 0xffff) << 32;
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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ret = b53_srab_op(dev, page, reg, 0);
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if (ret)
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goto err;
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*val = readl(regs + B53_SRAB_RD_L);
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*val += (u64)readl(regs + B53_SRAB_RD_H) << 32;
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel(value, regs + B53_SRAB_WD_L);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write16(struct b53_device *dev, u8 page, u8 reg,
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u16 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel(value, regs + B53_SRAB_WD_L);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write32(struct b53_device *dev, u8 page, u8 reg,
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u32 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel(value, regs + B53_SRAB_WD_L);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write48(struct b53_device *dev, u8 page, u8 reg,
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u64 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel((u32)value, regs + B53_SRAB_WD_L);
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writel((u16)(value >> 32), regs + B53_SRAB_WD_H);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static int b53_srab_write64(struct b53_device *dev, u8 page, u8 reg,
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u64 value)
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{
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struct b53_srab_priv *priv = dev->priv;
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u8 __iomem *regs = priv->regs;
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int ret = 0;
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ret = b53_srab_request_grant(dev);
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if (ret)
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goto err;
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writel((u32)value, regs + B53_SRAB_WD_L);
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writel((u32)(value >> 32), regs + B53_SRAB_WD_H);
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ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);
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err:
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b53_srab_release_grant(dev);
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return ret;
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}
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static irqreturn_t b53_srab_port_thread(int irq, void *dev_id)
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{
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struct b53_srab_port_priv *port = dev_id;
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struct b53_device *dev = port->dev;
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if (port->mode == PHY_INTERFACE_MODE_SGMII)
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b53_port_event(dev->ds, port->num);
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return IRQ_HANDLED;
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}
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static irqreturn_t b53_srab_port_isr(int irq, void *dev_id)
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{
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struct b53_srab_port_priv *port = dev_id;
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struct b53_device *dev = port->dev;
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struct b53_srab_priv *priv = dev->priv;
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/* Acknowledge the interrupt */
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writel(BIT(port->num), priv->regs + B53_SRAB_INTR);
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return IRQ_WAKE_THREAD;
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}
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#if IS_ENABLED(CONFIG_B53_SERDES)
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static u8 b53_srab_serdes_map_lane(struct b53_device *dev, int port)
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{
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struct b53_srab_priv *priv = dev->priv;
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struct b53_srab_port_priv *p = &priv->port_intrs[port];
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if (p->mode != PHY_INTERFACE_MODE_SGMII)
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return B53_INVALID_LANE;
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switch (port) {
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case 5:
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return 0;
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case 4:
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return 1;
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default:
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return B53_INVALID_LANE;
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}
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}
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#endif
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static int b53_srab_irq_enable(struct b53_device *dev, int port)
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{
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struct b53_srab_priv *priv = dev->priv;
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struct b53_srab_port_priv *p = &priv->port_intrs[port];
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int ret = 0;
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/* Interrupt is optional and was not specified, do not make
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* this fatal
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*/
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if (p->irq == -ENXIO)
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return ret;
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ret = request_threaded_irq(p->irq, b53_srab_port_isr,
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b53_srab_port_thread, 0,
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dev_name(dev->dev), p);
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if (!ret)
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p->irq_enabled = true;
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return ret;
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}
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static void b53_srab_irq_disable(struct b53_device *dev, int port)
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{
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struct b53_srab_priv *priv = dev->priv;
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struct b53_srab_port_priv *p = &priv->port_intrs[port];
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if (p->irq_enabled) {
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free_irq(p->irq, p);
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p->irq_enabled = false;
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}
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}
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static const struct b53_io_ops b53_srab_ops = {
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.read8 = b53_srab_read8,
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.read16 = b53_srab_read16,
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.read32 = b53_srab_read32,
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.read48 = b53_srab_read48,
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.read64 = b53_srab_read64,
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.write8 = b53_srab_write8,
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.write16 = b53_srab_write16,
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.write32 = b53_srab_write32,
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.write48 = b53_srab_write48,
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.write64 = b53_srab_write64,
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.irq_enable = b53_srab_irq_enable,
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.irq_disable = b53_srab_irq_disable,
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#if IS_ENABLED(CONFIG_B53_SERDES)
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.serdes_map_lane = b53_srab_serdes_map_lane,
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.serdes_link_state = b53_serdes_link_state,
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.serdes_config = b53_serdes_config,
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.serdes_an_restart = b53_serdes_an_restart,
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.serdes_link_set = b53_serdes_link_set,
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.serdes_phylink_validate = b53_serdes_phylink_validate,
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#endif
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};
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static const struct of_device_id b53_srab_of_match[] = {
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{ .compatible = "brcm,bcm53010-srab" },
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{ .compatible = "brcm,bcm53011-srab" },
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{ .compatible = "brcm,bcm53012-srab" },
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{ .compatible = "brcm,bcm53018-srab" },
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{ .compatible = "brcm,bcm53019-srab" },
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{ .compatible = "brcm,bcm5301x-srab" },
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{ .compatible = "brcm,bcm11360-srab", .data = (void *)BCM583XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58522-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58525-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58535-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58622-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58623-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm58625-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,bcm88312-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,cygnus-srab", .data = (void *)BCM583XX_DEVICE_ID },
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{ .compatible = "brcm,nsp-srab", .data = (void *)BCM58XX_DEVICE_ID },
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{ .compatible = "brcm,omega-srab", .data = (void *)BCM583XX_DEVICE_ID },
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{ /* sentinel */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, b53_srab_of_match);
|
|
|
|
static void b53_srab_intr_set(struct b53_srab_priv *priv, bool set)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = readl(priv->regs + B53_SRAB_CTRLS);
|
|
if (set)
|
|
reg |= B53_SRAB_CTRLS_HOST_INTR;
|
|
else
|
|
reg &= ~B53_SRAB_CTRLS_HOST_INTR;
|
|
writel(reg, priv->regs + B53_SRAB_CTRLS);
|
|
}
|
|
|
|
static void b53_srab_prepare_irq(struct platform_device *pdev)
|
|
{
|
|
struct b53_device *dev = platform_get_drvdata(pdev);
|
|
struct b53_srab_priv *priv = dev->priv;
|
|
struct b53_srab_port_priv *port;
|
|
unsigned int i;
|
|
char *name;
|
|
|
|
/* Clear all pending interrupts */
|
|
writel(0xffffffff, priv->regs + B53_SRAB_INTR);
|
|
|
|
for (i = 0; i < B53_N_PORTS; i++) {
|
|
port = &priv->port_intrs[i];
|
|
|
|
/* There is no port 6 */
|
|
if (i == 6)
|
|
continue;
|
|
|
|
name = kasprintf(GFP_KERNEL, "link_state_p%d", i);
|
|
if (!name)
|
|
return;
|
|
|
|
port->num = i;
|
|
port->dev = dev;
|
|
port->irq = platform_get_irq_byname_optional(pdev, name);
|
|
kfree(name);
|
|
}
|
|
|
|
b53_srab_intr_set(priv, true);
|
|
}
|
|
|
|
static void b53_srab_mux_init(struct platform_device *pdev)
|
|
{
|
|
struct b53_device *dev = platform_get_drvdata(pdev);
|
|
struct b53_srab_priv *priv = dev->priv;
|
|
struct b53_srab_port_priv *p;
|
|
unsigned int port;
|
|
u32 reg, off = 0;
|
|
int ret;
|
|
|
|
if (dev->pdata && dev->pdata->chip_id != BCM58XX_DEVICE_ID)
|
|
return;
|
|
|
|
priv->mux_config = devm_platform_ioremap_resource(pdev, 1);
|
|
if (IS_ERR(priv->mux_config))
|
|
return;
|
|
|
|
/* Obtain the port mux configuration so we know which lanes
|
|
* actually map to SerDes lanes
|
|
*/
|
|
for (port = 5; port > 3; port--, off += 4) {
|
|
p = &priv->port_intrs[port];
|
|
|
|
reg = readl(priv->mux_config + B53_MUX_CONFIG_P5 + off);
|
|
switch (reg & MUX_CONFIG_MASK) {
|
|
case MUX_CONFIG_SGMII:
|
|
p->mode = PHY_INTERFACE_MODE_SGMII;
|
|
ret = b53_serdes_init(dev, port);
|
|
if (ret)
|
|
continue;
|
|
break;
|
|
case MUX_CONFIG_MII_LITE:
|
|
p->mode = PHY_INTERFACE_MODE_MII;
|
|
break;
|
|
case MUX_CONFIG_GMII:
|
|
p->mode = PHY_INTERFACE_MODE_GMII;
|
|
break;
|
|
case MUX_CONFIG_RGMII:
|
|
p->mode = PHY_INTERFACE_MODE_RGMII;
|
|
break;
|
|
case MUX_CONFIG_INTERNAL:
|
|
p->mode = PHY_INTERFACE_MODE_INTERNAL;
|
|
break;
|
|
default:
|
|
p->mode = PHY_INTERFACE_MODE_NA;
|
|
break;
|
|
}
|
|
|
|
if (p->mode != PHY_INTERFACE_MODE_NA)
|
|
dev_info(&pdev->dev, "Port %d mode: %s\n",
|
|
port, phy_modes(p->mode));
|
|
}
|
|
}
|
|
|
|
static int b53_srab_probe(struct platform_device *pdev)
|
|
{
|
|
struct b53_platform_data *pdata = pdev->dev.platform_data;
|
|
struct device_node *dn = pdev->dev.of_node;
|
|
const struct of_device_id *of_id = NULL;
|
|
struct b53_srab_priv *priv;
|
|
struct b53_device *dev;
|
|
|
|
if (dn)
|
|
of_id = of_match_node(b53_srab_of_match, dn);
|
|
|
|
if (of_id) {
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
|
if (!pdata)
|
|
return -ENOMEM;
|
|
|
|
pdata->chip_id = (u32)(unsigned long)of_id->data;
|
|
}
|
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(priv->regs))
|
|
return PTR_ERR(priv->regs);
|
|
|
|
dev = b53_switch_alloc(&pdev->dev, &b53_srab_ops, priv);
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
|
|
if (pdata)
|
|
dev->pdata = pdata;
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
b53_srab_prepare_irq(pdev);
|
|
b53_srab_mux_init(pdev);
|
|
|
|
return b53_switch_register(dev);
|
|
}
|
|
|
|
static int b53_srab_remove(struct platform_device *pdev)
|
|
{
|
|
struct b53_device *dev = platform_get_drvdata(pdev);
|
|
struct b53_srab_priv *priv = dev->priv;
|
|
|
|
b53_srab_intr_set(priv, false);
|
|
if (dev)
|
|
b53_switch_remove(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver b53_srab_driver = {
|
|
.probe = b53_srab_probe,
|
|
.remove = b53_srab_remove,
|
|
.driver = {
|
|
.name = "b53-srab-switch",
|
|
.of_match_table = b53_srab_of_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(b53_srab_driver);
|
|
MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
|
|
MODULE_DESCRIPTION("B53 Switch Register Access Bridge Registers (SRAB) access driver");
|
|
MODULE_LICENSE("Dual BSD/GPL");
|