1bef016a5a
* Update registers * Update SREV values and add some PHY srevs * Prepare ath5k.h for newer radios etc Thanks to Atheros 's HAL source we now know for sure how many parts we have and what their SREV values are. We also have some updates on registers. Prepare ath5k for some major updates ;-) My previous mail had 2 more patches following (git log misusage), sorry for double posting ;-( Changes-Licensed-under: ISC Signed-Off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
316 lines
8.4 KiB
C
316 lines
8.4 KiB
C
/*
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* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
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* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/*************************************\
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* Attach/Detach Functions and helpers *
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\*************************************/
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#include <linux/pci.h>
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#include "ath5k.h"
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#include "reg.h"
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#include "debug.h"
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#include "base.h"
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/**
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* ath5k_hw_post - Power On Self Test helper function
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*
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* @ah: The &struct ath5k_hw
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*/
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static int ath5k_hw_post(struct ath5k_hw *ah)
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{
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int i, c;
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u16 cur_reg;
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u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
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u32 var_pattern;
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u32 static_pattern[4] = {
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0x55555555, 0xaaaaaaaa,
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0x66666666, 0x99999999
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};
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u32 init_val;
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u32 cur_val;
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for (c = 0; c < 2; c++) {
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cur_reg = regs[c];
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/* Save previous value */
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init_val = ath5k_hw_reg_read(ah, cur_reg);
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for (i = 0; i < 256; i++) {
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var_pattern = i << 16 | i;
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ath5k_hw_reg_write(ah, var_pattern, cur_reg);
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cur_val = ath5k_hw_reg_read(ah, cur_reg);
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if (cur_val != var_pattern) {
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ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
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return -EAGAIN;
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}
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/* Found on ndiswrapper dumps */
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var_pattern = 0x0039080f;
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ath5k_hw_reg_write(ah, var_pattern, cur_reg);
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}
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for (i = 0; i < 4; i++) {
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var_pattern = static_pattern[i];
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ath5k_hw_reg_write(ah, var_pattern, cur_reg);
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cur_val = ath5k_hw_reg_read(ah, cur_reg);
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if (cur_val != var_pattern) {
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ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
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return -EAGAIN;
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}
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/* Found on ndiswrapper dumps */
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var_pattern = 0x003b080f;
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ath5k_hw_reg_write(ah, var_pattern, cur_reg);
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}
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/* Restore previous value */
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ath5k_hw_reg_write(ah, init_val, cur_reg);
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}
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return 0;
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}
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/**
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* ath5k_hw_attach - Check if hw is supported and init the needed structs
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*
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* @sc: The &struct ath5k_softc we got from the driver's attach function
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* @mac_version: The mac version id (check out ath5k.h) based on pci id
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*
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* Check if the device is supported, perform a POST and initialize the needed
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* structs. Returns -ENOMEM if we don't have memory for the needed structs,
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* -ENODEV if the device is not supported or prints an error msg if something
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* else went wrong.
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*/
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struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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{
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struct ath5k_hw *ah;
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struct pci_dev *pdev = sc->pdev;
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u8 mac[ETH_ALEN];
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int ret;
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u32 srev;
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/*If we passed the test malloc a ath5k_hw struct*/
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ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
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if (ah == NULL) {
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ret = -ENOMEM;
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ATH5K_ERR(sc, "out of memory\n");
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goto err;
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}
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ah->ah_sc = sc;
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ah->ah_iobase = sc->iobase;
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/*
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* HW information
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*/
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ah->ah_op_mode = NL80211_IFTYPE_STATION;
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ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
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ah->ah_turbo = false;
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ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
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ah->ah_imr = 0;
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ah->ah_atim_window = 0;
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ah->ah_aifs = AR5K_TUNE_AIFS;
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ah->ah_cw_min = AR5K_TUNE_CWMIN;
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ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
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ah->ah_software_retry = false;
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ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
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/*
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* Set the mac revision based on the pci id
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*/
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ah->ah_version = mac_version;
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/*Fill the ath5k_hw struct with the needed functions*/
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ret = ath5k_hw_init_desc_functions(ah);
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if (ret)
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goto err_free;
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/* Bring device out of sleep and reset it's units */
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ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, true);
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if (ret)
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goto err_free;
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/* Get MAC, PHY and RADIO revisions */
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srev = ath5k_hw_reg_read(ah, AR5K_SREV);
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ah->ah_mac_srev = srev;
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ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
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ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
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ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
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0xffffffff;
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ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_5GHZ);
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if (ah->ah_version == AR5K_AR5210)
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ah->ah_radio_2ghz_revision = 0;
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else
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ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_2GHZ);
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/* Return on unsuported chips (unsupported eeprom etc) */
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if ((srev >= AR5K_SREV_AR5416) &&
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(srev < AR5K_SREV_AR2425)) {
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ATH5K_ERR(sc, "Device not yet supported.\n");
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ret = -ENODEV;
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goto err_free;
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} else if (srev == AR5K_SREV_AR2425) {
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ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
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}
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/* Identify single chip solutions */
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if (((srev <= AR5K_SREV_AR5414) &&
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(srev >= AR5K_SREV_AR2413)) ||
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(srev == AR5K_SREV_AR2425)) {
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ah->ah_single_chip = true;
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} else {
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ah->ah_single_chip = false;
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}
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/* Single chip radio */
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if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
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ah->ah_radio_2ghz_revision = 0;
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/* Identify the radio chip*/
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if (ah->ah_version == AR5K_AR5210) {
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ah->ah_radio = AR5K_RF5110;
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/*
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* Register returns 0x0/0x04 for radio revision
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* so ath5k_hw_radio_revision doesn't parse the value
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* correctly. For now we are based on mac's srev to
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* identify RF2425 radio.
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*/
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} else if (srev == AR5K_SREV_AR2425) {
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ah->ah_radio = AR5K_RF2425;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
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ah->ah_radio = AR5K_RF5111;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_2413) {
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ah->ah_radio = AR5K_RF5112;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5413) {
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ah->ah_radio = AR5K_RF2413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_2316) {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
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/* AR5424 */
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if (srev >= AR5K_SREV_AR5424) {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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/* AR2424 */
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} else {
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ah->ah_radio = AR5K_RF2413; /* For testing */
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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}
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}
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ah->ah_phy = AR5K_PHY(0);
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/*
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* Write PCI-E power save settings
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*/
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if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
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ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
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ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
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ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
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ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
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ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
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ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
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ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
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ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
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ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
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ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
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}
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/*
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* POST
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*/
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ret = ath5k_hw_post(ah);
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if (ret)
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goto err_free;
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/* Write AR5K_PCICFG_UNK on 2112B and later chips */
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if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B ||
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srev > AR5K_SREV_AR2413) {
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ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);
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}
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/*
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* Get card capabilities, values, ...
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*/
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ret = ath5k_eeprom_init(ah);
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if (ret) {
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ATH5K_ERR(sc, "unable to init EEPROM\n");
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goto err_free;
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}
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/* Get misc capabilities */
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ret = ath5k_hw_set_capabilities(ah);
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if (ret) {
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ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
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sc->pdev->device);
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goto err_free;
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}
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/* Get MAC address */
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ret = ath5k_eeprom_read_mac(ah, mac);
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if (ret) {
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ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
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sc->pdev->device);
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goto err_free;
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}
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ath5k_hw_set_lladdr(ah, mac);
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/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
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memset(ah->ah_bssid, 0xff, ETH_ALEN);
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ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
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ath5k_hw_set_opmode(ah);
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ath5k_hw_set_rfgain_opt(ah);
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return ah;
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err_free:
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kfree(ah);
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err:
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return ERR_PTR(ret);
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}
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/**
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* ath5k_hw_detach - Free the ath5k_hw struct
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*
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* @ah: The &struct ath5k_hw
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*/
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void ath5k_hw_detach(struct ath5k_hw *ah)
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{
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ATH5K_TRACE(ah->ah_sc);
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__set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
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if (ah->ah_rf_banks != NULL)
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kfree(ah->ah_rf_banks);
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/* assume interrupts are down */
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kfree(ah);
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}
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