Nicolas Pitre 1bb772679f [ARM] Feroceon: add highmem support to L2 cache handling code ... The choice is between looping over the physical range and performing single cache line operations, or to map highmem pages somewhere, as cache range ops are possible only on virtual addresses. Because L2 range ops are much faster, we go with the later by factoring the physical-to-virtual address conversion and use a fixmap entry for it in the HIGHMEM case. Possible future optimizations to avoid the pte setup cost: - do the pte setup for highmem pages only - determine a threshold for doing a line-by-line processing on physical addresses when the range is small Signed-off-by: Nicolas Pitre <nico@marvell.com>		2009-03-15 21:01:21 -04:00
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asm	[ARM] Feroceon: add highmem support to L2 cache handling code	2009-03-15 21:01:21 -04:00