Mahesh Kumar 1b0008450f drm/i915/cnl: Fix PORT_TX_DW5/7 register address ... Register Address for CNL_PORT_DW5_LN0_D is 0x162E54, but current code is defining it as 0x162ED4. Similarly for CNL_PORT_DW7_LN0_D register address is defined 0x162EDC instead of 0x162E5C, fix it. Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Fixes: 04416108cc ("drm/i915/cnl: Add registers related to voltage swing sequences.") Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180215095643.3844-2-mahesh1.kumar@intel.com (cherry picked from commit e103962611) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>		2018-02-28 11:10:37 -08:00
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drm	drm/i915/cnl: Fix PORT_TX_DW5/7 register address	2018-02-28 11:10:37 -08:00
host1x	gpu: host1x: Use IOMMU groups	2017-12-21 14:52:36 +01:00
ipu-v3	gpu: ipu-csi: add 10/12-bit grayscale support to mbus_code_to_bus_cfg	2018-02-19 15:13:05 +01:00
vga	vfs: do bulk POLL* -> EPOLL* replacement	2018-02-11 14:34:03 -08:00
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