Bhawanpreet Lakha 9713158cb2 drm/amdgpu: Add and use seperate reg headers for dcn302 ... Currently we are using dcn3 reg headers for dcn302. The offsets are different between the two so they need seperate headers. Add dcn302 header files and use these instead of dcn3 header Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-11-10 14:15:08 -05:00
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athub	drm/amdgpu: Add ATHUB 2.1 header files (v2)	2020-06-03 13:51:55 -04:00
bif
clk	drm/amdgpu: add vangogh asic header files (v2)	2020-10-05 15:14:02 -04:00
dce	drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling	2020-08-26 16:40:18 -04:00
dcn	drm/amdgpu: Add and use seperate reg headers for dcn302	2020-11-10 14:15:08 -05:00
df	drm/amdgpu: added support to get mGPU DRAM base	2020-01-22 16:34:07 -05:00
dpcs	drm/amdgpu: add dpcs20 registers	2019-12-18 16:09:06 -05:00
gc	drm/amdgpu: add GC 10.3 NOALLOC registers	2020-10-23 15:33:47 -04:00
gca
gmc
hdp
mmhub	drm/amdgpu: add vangogh asic header files (v2)	2020-10-05 15:14:02 -04:00
mp	drm/amdgpu: add vangogh asic header files (v2)	2020-10-05 15:14:02 -04:00
nbif	drm/amdgpu: cleanup all virtualization detection routine	2020-04-01 14:44:42 -04:00
nbio	drm/amdgpu: add vangogh asic header files (v2)	2020-10-05 15:14:02 -04:00
oss
pwr	drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own header	2020-04-01 14:44:43 -04:00
rsmu
sdma0
sdma1
sdma2
sdma3
sdma4
sdma5
sdma6
sdma7
smu
smuio	drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)	2020-04-01 14:44:43 -04:00
thm
umc	drm/amdgpu: add umc v8_7_0 IP headers	2020-07-27 16:22:46 -04:00
uvd	drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700	2020-09-17 17:59:54 -04:00
vce
vcn	drm/amdgpu: add VCN 3.0 AV1 registers	2020-09-17 18:01:46 -04:00
wafl	drm/amdgpu: add wafl2 ip headers	2020-03-06 14:31:21 -05:00
xgmi	drm/amdgpu: add xgmi ip headers	2020-03-06 14:31:00 -05:00