d68fe15b18
mdp5_enable/disable calls are scattered all around in the MDP5 code. Use the pm_runtime_get/put calls here instead, and populate the runtime PM suspend/resume ops to manage the clocks. About the overall design: MDP5 is a child of the top level MDSS device. MDSS is also the parent to DSI, HDMI and other interfaces. When we enable MDP5's power domain, we end up enabling MDSS's PD too. It is only MDSS's PD that actually controlls the GDSC HW. Therefore, calling runtime_get/put on the MDP5 device is like just requesting a vote to enable/disable the GDSC. Functionally, replacing the clock enable/disable calls with the RPM API can result in the power domain (GDSC) state being toggled if no other child isn't powered on. This can result in the register context being lost. We make sure (in future commits) that code paths don't end up configuring registers and then later lose state, resulting in a bad HW state. For now, we've replaced each mdp5_enable/disable with runtime_get/put API. We could optimize things later by removing runtime_get/put calls which don't really need to be there. This could prevent unnecessary toggling of the power domain and clocks. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/irq.h>
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#include <drm/drm_print.h>
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#include "msm_drv.h"
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#include "mdp5_kms.h"
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void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
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uint32_t old_irqmask)
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{
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mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_CLEAR,
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irqmask ^ (irqmask & old_irqmask));
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mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
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}
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static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
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{
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struct mdp5_kms *mdp5_kms = container_of(irq, struct mdp5_kms, error_handler);
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static DEFINE_RATELIMIT_STATE(rs, 5*HZ, 1);
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extern bool dumpstate;
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DRM_ERROR_RATELIMITED("errors: %08x\n", irqstatus);
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if (dumpstate && __ratelimit(&rs)) {
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struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev);
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drm_state_dump(mdp5_kms->dev, &p);
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if (mdp5_kms->smp)
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mdp5_smp_dump(mdp5_kms->smp, &p);
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}
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}
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void mdp5_irq_preinstall(struct msm_kms *kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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struct device *dev = &mdp5_kms->pdev->dev;
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pm_runtime_get_sync(dev);
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mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);
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mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
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pm_runtime_put_autosuspend(dev);
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}
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int mdp5_irq_postinstall(struct msm_kms *kms)
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{
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struct mdp_kms *mdp_kms = to_mdp_kms(kms);
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
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struct device *dev = &mdp5_kms->pdev->dev;
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struct mdp_irq *error_handler = &mdp5_kms->error_handler;
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error_handler->irq = mdp5_irq_error_handler;
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error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN |
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MDP5_IRQ_INTF1_UNDER_RUN |
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MDP5_IRQ_INTF2_UNDER_RUN |
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MDP5_IRQ_INTF3_UNDER_RUN;
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pm_runtime_get_sync(dev);
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mdp_irq_register(mdp_kms, error_handler);
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pm_runtime_put_autosuspend(dev);
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return 0;
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}
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void mdp5_irq_uninstall(struct msm_kms *kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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struct device *dev = &mdp5_kms->pdev->dev;
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pm_runtime_get_sync(dev);
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mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
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pm_runtime_put_autosuspend(dev);
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}
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irqreturn_t mdp5_irq(struct msm_kms *kms)
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{
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struct mdp_kms *mdp_kms = to_mdp_kms(kms);
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
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struct drm_device *dev = mdp5_kms->dev;
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struct msm_drm_private *priv = dev->dev_private;
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unsigned int id;
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uint32_t status, enable;
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enable = mdp5_read(mdp5_kms, REG_MDP5_INTR_EN);
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status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS) & enable;
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mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);
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VERB("status=%08x", status);
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mdp_dispatch_irqs(mdp_kms, status);
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for (id = 0; id < priv->num_crtcs; id++)
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if (status & mdp5_crtc_vblank(priv->crtcs[id]))
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drm_handle_vblank(dev, id);
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return IRQ_HANDLED;
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}
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int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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struct device *dev = &mdp5_kms->pdev->dev;
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pm_runtime_get_sync(dev);
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mdp_update_vblank_mask(to_mdp_kms(kms),
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mdp5_crtc_vblank(crtc), true);
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pm_runtime_put_autosuspend(dev);
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return 0;
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}
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void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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struct device *dev = &mdp5_kms->pdev->dev;
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pm_runtime_get_sync(dev);
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mdp_update_vblank_mask(to_mdp_kms(kms),
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mdp5_crtc_vblank(crtc), false);
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pm_runtime_put_autosuspend(dev);
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}
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