- support for HSDK board hosting a Quad core HS38x4 based SoC running @ 1 GHz (and some prerrquisite changes such as ability to scoot the kernel code/data from start of memory map etc) - Quite a few updates for EZChip (Mellanox) platform - Fixes to fault/exception printing -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZstaxAAoJEGnX8d3iisJe5I0QAIExIdU5/V/bgJ7EJJaa6qW4 VxB5HXzbwOuIx/3i/uv4AwBIoeZIzuRQnjwf2dzTJms5vjT2zR08DGYIBmtSAA23 ZUmpZVd865IItLCRM7WOerP6B6gaHaObzNlZoo2d8rVnz0fruc5Td4PDC1Esfs7D vA4aITbiG6FsJMYFeYR6IKJbM8D1CmB2Gm1gEPIifniJ9dy/V9Xi5ttvISpVJSNx QMb6PDHVEpkOBypUEJKeoClFZlkeqscejjXmZ3QrhoeHM//3hX8MdvyvFBmoCY4t YpmmrfmoCupwFFn7+XDwYqDyYvJk/H84n64tUcpM7PLqCuw4BaMhd3KTjkTwvsnN H5NAhqbHIW3r4a9esn53yvgY8zk9i6U7qmhKpEwkUQTtUZ7XrdfL1H1t08cqtxPX /eFBkeKNshJy8EU02MewtxvWXON3RoJC3qgHoLkrj+iq5HTQjaDEahbQNm+rnXFI EdRMBwPX2sXOvB/m/jQYjz6QM1QTl6zHy+tXbBpATIqgRxsp6SIInqGmq7fC032a K7zPWo2Vf2LLl4ifhFJaYwbrQotqDGe/F72K1C5RcWKLnhMPdLgZ4Lwf0NcJTeDt DjmqUFXwNdQ2Ydw0B9JxeTddVCzdLHPQqxOOvvBI0vvgsF8AFmAmx2QhMdQTsZJr 73mD3udrQN48yYzAIZQf =w8CJ -----END PGP SIGNATURE----- Merge tag 'arc-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC updates from Vineet Gupta: - Support for HSDK board hosting a Quad core HS38x4 based SoC running @1GHz (and some prerrquisite changes such as ability to scoot the kernel code/data from start of memory map etc) - Quite a few updates for EZChip (Mellanox) platform - Fixes to fault/exception printing * tag 'arc-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (26 commits) ARC: Re-enable MMU upon Machine Check exception ARC: Show fault information passed to show_kernel_fault_diag() ARC: [plat-hsdk] initial port for HSDK board ARC: mm: Decouple RAM base address from kernel link address ARCv2: IOC: Tighten up the contraints (specifically base / size alignment) ARC: [plat-axs103] refactor the DT fudging code ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk ARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk setting ARCv2: SLC: provide a line based flush routine for debugging ARC: Hardcode ARCH_DMA_MINALIGN to max line length we may have ARC: [plat-eznps] handle extra aux regs #2: kernel/entry exit ARC: [plat-eznps] handle extra aux regs #1: save/restore on context switch ARC: [plat-eznps] avoid toggling of DPC register ARC: [plat-eznps] Update the init sequence of aux regs per cpu. ARC: [plat-eznps] new command line argument for HW scheduler at MTM ARC: set boot print log level to PR_INFO ARC: [plat-eznps] Handle user memory error same in simulation and silicon ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task ARC: create cpu specific version of arch_cpu_idle() ARC: [plat-eznps] spinlock aware for MTM ...
424 lines
9.2 KiB
C
424 lines
9.2 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/spinlock_types.h>
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#include <asm/processor.h>
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#include <asm/barrier.h>
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#define arch_spin_is_locked(x) ((x)->slock != __ARCH_SPIN_LOCK_UNLOCKED__)
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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#ifdef CONFIG_ARC_HAS_LLSC
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int val;
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smp_mb();
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__asm__ __volatile__(
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"1: llock %[val], [%[slock]] \n"
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" breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */
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" scond %[LOCKED], [%[slock]] \n" /* acquire */
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [slock] "r" (&(lock->slock)),
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[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
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: "memory", "cc");
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int val, got_it = 0;
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smp_mb();
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__asm__ __volatile__(
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"1: llock %[val], [%[slock]] \n"
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" breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */
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" scond %[LOCKED], [%[slock]] \n" /* acquire */
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" bnz 1b \n"
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" mov %[got_it], 1 \n"
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"4: \n"
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" \n"
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: [val] "=&r" (val),
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[got_it] "+&r" (got_it)
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: [slock] "r" (&(lock->slock)),
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[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
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: "memory", "cc");
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smp_mb();
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return got_it;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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smp_mb();
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lock->slock = __ARCH_SPIN_LOCK_UNLOCKED__;
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smp_mb();
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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* Unfair locking as Writers could be starved indefinitely by Reader(s)
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned int val;
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smp_mb();
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/*
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* zero means writer holds the lock exclusively, deny Reader.
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* Otherwise grant lock to first/subseq reader
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*
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* if (rw->counter > 0) {
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* rw->counter--;
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* ret = 1;
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* }
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*/
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" brls %[val], %[WR_LOCKED], 1b\n" /* <= 0: spin while write locked */
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" sub %[val], %[val], 1 \n" /* reader lock */
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [rwlock] "r" (&(rw->counter)),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned int val, got_it = 0;
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smp_mb();
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" brls %[val], %[WR_LOCKED], 4f\n" /* <= 0: already write locked, bail */
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" sub %[val], %[val], 1 \n" /* counter-- */
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n" /* retry if collided with someone */
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" mov %[got_it], 1 \n"
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" \n"
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"4: ; --- done --- \n"
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: [val] "=&r" (val),
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[got_it] "+&r" (got_it)
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: [rwlock] "r" (&(rw->counter)),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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return got_it;
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned int val;
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smp_mb();
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/*
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* If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
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* deny writer. Otherwise if unlocked grant to writer
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* Hence the claim that Linux rwlocks are unfair to writers.
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* (can be starved for an indefinite time by readers).
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*
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* if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
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* rw->counter = 0;
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* ret = 1;
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* }
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*/
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" brne %[val], %[UNLOCKED], 1b \n" /* while !UNLOCKED spin */
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" mov %[val], %[WR_LOCKED] \n"
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [rwlock] "r" (&(rw->counter)),
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[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned int val, got_it = 0;
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smp_mb();
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" brne %[val], %[UNLOCKED], 4f \n" /* !UNLOCKED, bail */
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" mov %[val], %[WR_LOCKED] \n"
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n" /* retry if collided with someone */
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" mov %[got_it], 1 \n"
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" \n"
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"4: ; --- done --- \n"
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: [val] "=&r" (val),
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[got_it] "+&r" (got_it)
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: [rwlock] "r" (&(rw->counter)),
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[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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return got_it;
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned int val;
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smp_mb();
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/*
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* rw->counter++;
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*/
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" add %[val], %[val], 1 \n"
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [rwlock] "r" (&(rw->counter))
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: "memory", "cc");
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smp_mb();
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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smp_mb();
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rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
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smp_mb();
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int val = __ARCH_SPIN_LOCK_LOCKED__;
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/*
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* This smp_mb() is technically superfluous, we only need the one
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* after the lock for providing the ACQUIRE semantics.
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* However doing the "right" thing was regressing hackbench
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* so keeping this, pending further investigation
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*/
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smp_mb();
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__asm__ __volatile__(
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"1: ex %0, [%1] \n"
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#ifdef CONFIG_EZNPS_MTM_EXT
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" .word %3 \n"
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#endif
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" breq %0, %2, 1b \n"
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: "+&r" (val)
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: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
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#ifdef CONFIG_EZNPS_MTM_EXT
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, "i"(CTOP_INST_SCHD_RW)
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#endif
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: "memory");
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/*
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* ACQUIRE barrier to ensure load/store after taking the lock
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* don't "bleed-up" out of the critical section (leak-in is allowed)
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* http://www.spinics.net/lists/kernel/msg2010409.html
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*
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* ARCv2 only has load-load, store-store and all-all barrier
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* thus need the full all-all barrier
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*/
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int val = __ARCH_SPIN_LOCK_LOCKED__;
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smp_mb();
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__asm__ __volatile__(
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"1: ex %0, [%1] \n"
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: "+r" (val)
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: "r"(&(lock->slock))
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: "memory");
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smp_mb();
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return (val == __ARCH_SPIN_LOCK_UNLOCKED__);
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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unsigned int val = __ARCH_SPIN_LOCK_UNLOCKED__;
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/*
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* RELEASE barrier: given the instructions avail on ARCv2, full barrier
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* is the only option
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*/
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smp_mb();
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/*
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* EX is not really required here, a simple STore of 0 suffices.
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* However this causes tasklist livelocks in SystemC based SMP virtual
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* platforms where the systemc core scheduler uses EX as a cue for
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* moving to next core. Do a git log of this file for details
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*/
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__asm__ __volatile__(
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" ex %0, [%1] \n"
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: "+r" (val)
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: "r"(&(lock->slock))
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: "memory");
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/*
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* superfluous, but keeping for now - see pairing version in
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* arch_spin_lock above
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*/
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smp_mb();
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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* Unfair locking as Writers could be starved indefinitely by Reader(s)
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*
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* The spinlock itself is contained in @counter and access to it is
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* serialized with @lock_mutex.
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*/
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/* 1 - lock taken successfully */
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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int ret = 0;
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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/*
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* zero means writer holds the lock exclusively, deny Reader.
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* Otherwise grant lock to first/subseq reader
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*/
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if (rw->counter > 0) {
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rw->counter--;
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ret = 1;
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}
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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smp_mb();
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return ret;
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}
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/* 1 - lock taken successfully */
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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int ret = 0;
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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/*
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* If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
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* deny writer. Otherwise if unlocked grant to writer
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* Hence the claim that Linux rwlocks are unfair to writers.
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* (can be starved for an indefinite time by readers).
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*/
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if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
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rw->counter = 0;
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ret = 1;
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}
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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return ret;
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}
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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while (!arch_read_trylock(rw))
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cpu_relax();
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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while (!arch_write_trylock(rw))
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cpu_relax();
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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rw->counter++;
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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}
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#endif
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#define arch_read_can_lock(x) ((x)->counter > 0)
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#define arch_write_can_lock(x) ((x)->counter == __ARCH_RW_LOCK_UNLOCKED__)
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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#endif /* __ASM_SPINLOCK_H */
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