Satheeshakrishna M 1ab23380f8 drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9 ... PORT_CLK_SEL programming is needed only on HSW/BDW. v2: - don't program PORT_CLK_SEL from mst encoders either (imre) v3: - fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien) Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2015-04-16 11:29:05 +02:00
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drm	drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9	2015-04-16 11:29:05 +02:00
host1x	gpu: host1x: Export host1x_syncpt_read()	2015-04-02 18:46:20 +02:00
ipu-v3	gpu: ipu-v3: turns out the IPU can only downsize 4:1	2015-03-31 12:03:55 +02:00
vga
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00