forked from Minki/linux
c4158ff536
This patch adds the __irq_entry annotation to the default x86 platform IRQ handlers. ftrace's function_graph tracer uses the __irq_entry annotation to notify the entry and return of IRQ handlers. For example, before the patch: 354549.667252 | 3) d..1 | default_idle_call() { 354549.667252 | 3) d..1 | arch_cpu_idle() { 354549.667253 | 3) d..1 | default_idle() { 354549.696886 | 3) d..1 | smp_trace_reschedule_interrupt() { 354549.696886 | 3) d..1 | irq_enter() { 354549.696886 | 3) d..1 | rcu_irq_enter() { After the patch: 366416.254476 | 3) d..1 | arch_cpu_idle() { 366416.254476 | 3) d..1 | default_idle() { 366416.261566 | 3) d..1 ==========> | 366416.261566 | 3) d..1 | smp_trace_reschedule_interrupt() { 366416.261566 | 3) d..1 | irq_enter() { 366416.261566 | 3) d..1 | rcu_irq_enter() { KASAN also uses this annotation. The smp_apic_timer_interrupt() was already annotated. Signed-off-by: Daniel Bristot de Oliveira <bristot@redhat.com> Acked-by: Steven Rostedt (VMware) <rostedt@goodmis.org> Cc: Aaron Lu <aaron.lu@intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Baoquan He <bhe@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Claudio Fontana <claudio.fontana@huawei.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Dou Liyang <douly.fnst@cn.fujitsu.com> Cc: Gu Zheng <guz.fnst@cn.fujitsu.com> Cc: Hidehiro Kawai <hidehiro.kawai.ez@hitachi.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Nicolai Stange <nicstange@gmail.com> Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Wanpeng Li <wanpeng.li@hotmail.com> Cc: linux-edac@vger.kernel.org Link: http://lkml.kernel.org/r/059fdf437c2f0c09b13c18c8fe4e69999d3ffe69.1483528431.git.bristot@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
974 lines
25 KiB
C
974 lines
25 KiB
C
/*
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* Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
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*
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* Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
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* Moved from arch/x86/kernel/apic/io_apic.c.
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* Jiang Liu <jiang.liu@linux.intel.com>
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* Enable support of hierarchical irqdomains
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/compiler.h>
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#include <linux/slab.h>
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#include <asm/irqdomain.h>
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#include <asm/hw_irq.h>
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#include <asm/apic.h>
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#include <asm/i8259.h>
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#include <asm/desc.h>
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#include <asm/irq_remapping.h>
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struct apic_chip_data {
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struct irq_cfg cfg;
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cpumask_var_t domain;
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cpumask_var_t old_domain;
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u8 move_in_progress : 1;
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};
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struct irq_domain *x86_vector_domain;
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EXPORT_SYMBOL_GPL(x86_vector_domain);
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static DEFINE_RAW_SPINLOCK(vector_lock);
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static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask;
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static struct irq_chip lapic_controller;
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#ifdef CONFIG_X86_IO_APIC
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static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
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#endif
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void lock_vector_lock(void)
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{
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/* Used to the online set of cpus does not change
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* during assign_irq_vector.
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*/
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raw_spin_lock(&vector_lock);
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}
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void unlock_vector_lock(void)
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{
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raw_spin_unlock(&vector_lock);
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}
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static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
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{
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if (!irq_data)
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return NULL;
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while (irq_data->parent_data)
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irq_data = irq_data->parent_data;
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return irq_data->chip_data;
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}
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struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
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{
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struct apic_chip_data *data = apic_chip_data(irq_data);
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return data ? &data->cfg : NULL;
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}
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EXPORT_SYMBOL_GPL(irqd_cfg);
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struct irq_cfg *irq_cfg(unsigned int irq)
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{
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return irqd_cfg(irq_get_irq_data(irq));
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}
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static struct apic_chip_data *alloc_apic_chip_data(int node)
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{
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struct apic_chip_data *data;
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data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
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if (!data)
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return NULL;
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if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
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goto out_data;
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if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
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goto out_domain;
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return data;
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out_domain:
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free_cpumask_var(data->domain);
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out_data:
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kfree(data);
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return NULL;
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}
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static void free_apic_chip_data(struct apic_chip_data *data)
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{
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if (data) {
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free_cpumask_var(data->domain);
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free_cpumask_var(data->old_domain);
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kfree(data);
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}
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}
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static int __assign_irq_vector(int irq, struct apic_chip_data *d,
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const struct cpumask *mask)
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{
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/*
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* NOTE! The local APIC isn't very good at handling
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* multiple interrupts at the same interrupt level.
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* As the interrupt level is determined by taking the
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* vector number and shifting that right by 4, we
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* want to spread these out a bit so that they don't
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* all fall in the same interrupt level.
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*
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* Also, we've got to be careful not to trash gate
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* 0x80, because int 0x80 is hm, kind of importantish. ;)
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*/
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static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
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static int current_offset = VECTOR_OFFSET_START % 16;
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int cpu, vector;
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/*
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* If there is still a move in progress or the previous move has not
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* been cleaned up completely, tell the caller to come back later.
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*/
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if (d->move_in_progress ||
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cpumask_intersects(d->old_domain, cpu_online_mask))
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return -EBUSY;
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/* Only try and allocate irqs on cpus that are present */
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cpumask_clear(d->old_domain);
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cpumask_clear(searched_cpumask);
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cpu = cpumask_first_and(mask, cpu_online_mask);
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while (cpu < nr_cpu_ids) {
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int new_cpu, offset;
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/* Get the possible target cpus for @mask/@cpu from the apic */
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apic->vector_allocation_domain(cpu, vector_cpumask, mask);
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/*
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* Clear the offline cpus from @vector_cpumask for searching
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* and verify whether the result overlaps with @mask. If true,
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* then the call to apic->cpu_mask_to_apicid_and() will
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* succeed as well. If not, no point in trying to find a
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* vector in this mask.
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*/
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cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask);
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if (!cpumask_intersects(vector_searchmask, mask))
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goto next_cpu;
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if (cpumask_subset(vector_cpumask, d->domain)) {
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if (cpumask_equal(vector_cpumask, d->domain))
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goto success;
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/*
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* Mark the cpus which are not longer in the mask for
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* cleanup.
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*/
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cpumask_andnot(d->old_domain, d->domain, vector_cpumask);
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vector = d->cfg.vector;
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goto update;
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}
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vector = current_vector;
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offset = current_offset;
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next:
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vector += 16;
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if (vector >= first_system_vector) {
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offset = (offset + 1) % 16;
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vector = FIRST_EXTERNAL_VECTOR + offset;
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}
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/* If the search wrapped around, try the next cpu */
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if (unlikely(current_vector == vector))
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goto next_cpu;
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if (test_bit(vector, used_vectors))
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goto next;
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for_each_cpu(new_cpu, vector_searchmask) {
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if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
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goto next;
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}
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/* Found one! */
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current_vector = vector;
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current_offset = offset;
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/* Schedule the old vector for cleanup on all cpus */
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if (d->cfg.vector)
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cpumask_copy(d->old_domain, d->domain);
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for_each_cpu(new_cpu, vector_searchmask)
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per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
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goto update;
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next_cpu:
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/*
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* We exclude the current @vector_cpumask from the requested
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* @mask and try again with the next online cpu in the
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* result. We cannot modify @mask, so we use @vector_cpumask
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* as a temporary buffer here as it will be reassigned when
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* calling apic->vector_allocation_domain() above.
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*/
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cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask);
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cpumask_andnot(vector_cpumask, mask, searched_cpumask);
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cpu = cpumask_first_and(vector_cpumask, cpu_online_mask);
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continue;
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}
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return -ENOSPC;
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update:
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/*
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* Exclude offline cpus from the cleanup mask and set the
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* move_in_progress flag when the result is not empty.
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*/
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cpumask_and(d->old_domain, d->old_domain, cpu_online_mask);
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d->move_in_progress = !cpumask_empty(d->old_domain);
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d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0;
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d->cfg.vector = vector;
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cpumask_copy(d->domain, vector_cpumask);
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success:
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/*
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* Cache destination APIC IDs into cfg->dest_apicid. This cannot fail
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* as we already established, that mask & d->domain & cpu_online_mask
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* is not empty.
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*/
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BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain,
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&d->cfg.dest_apicid));
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return 0;
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}
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static int assign_irq_vector(int irq, struct apic_chip_data *data,
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const struct cpumask *mask)
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{
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int err;
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unsigned long flags;
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raw_spin_lock_irqsave(&vector_lock, flags);
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err = __assign_irq_vector(irq, data, mask);
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raw_spin_unlock_irqrestore(&vector_lock, flags);
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return err;
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}
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static int assign_irq_vector_policy(int irq, int node,
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struct apic_chip_data *data,
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struct irq_alloc_info *info)
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{
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if (info && info->mask)
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return assign_irq_vector(irq, data, info->mask);
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if (node != NUMA_NO_NODE &&
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assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
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return 0;
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return assign_irq_vector(irq, data, apic->target_cpus());
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}
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static void clear_irq_vector(int irq, struct apic_chip_data *data)
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{
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struct irq_desc *desc;
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int cpu, vector;
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if (!data->cfg.vector)
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return;
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vector = data->cfg.vector;
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for_each_cpu_and(cpu, data->domain, cpu_online_mask)
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per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
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data->cfg.vector = 0;
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cpumask_clear(data->domain);
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/*
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* If move is in progress or the old_domain mask is not empty,
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* i.e. the cleanup IPI has not been processed yet, we need to remove
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* the old references to desc from all cpus vector tables.
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*/
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if (!data->move_in_progress && cpumask_empty(data->old_domain))
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return;
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desc = irq_to_desc(irq);
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for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
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for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
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vector++) {
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if (per_cpu(vector_irq, cpu)[vector] != desc)
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continue;
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per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
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break;
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}
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}
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data->move_in_progress = 0;
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}
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void init_irq_alloc_info(struct irq_alloc_info *info,
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const struct cpumask *mask)
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{
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memset(info, 0, sizeof(*info));
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info->mask = mask;
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}
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void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
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{
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if (src)
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*dst = *src;
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else
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memset(dst, 0, sizeof(*dst));
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}
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static void x86_vector_free_irqs(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct apic_chip_data *apic_data;
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struct irq_data *irq_data;
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unsigned long flags;
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int i;
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for (i = 0; i < nr_irqs; i++) {
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irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
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if (irq_data && irq_data->chip_data) {
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raw_spin_lock_irqsave(&vector_lock, flags);
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clear_irq_vector(virq + i, irq_data->chip_data);
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apic_data = irq_data->chip_data;
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irq_domain_reset_irq_data(irq_data);
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raw_spin_unlock_irqrestore(&vector_lock, flags);
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free_apic_chip_data(apic_data);
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#ifdef CONFIG_X86_IO_APIC
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if (virq + i < nr_legacy_irqs())
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legacy_irq_data[virq + i] = NULL;
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#endif
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}
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}
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}
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static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct irq_alloc_info *info = arg;
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struct apic_chip_data *data;
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struct irq_data *irq_data;
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int i, err, node;
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if (disable_apic)
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return -ENXIO;
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/* Currently vector allocator can't guarantee contiguous allocations */
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if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
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return -ENOSYS;
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for (i = 0; i < nr_irqs; i++) {
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irq_data = irq_domain_get_irq_data(domain, virq + i);
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BUG_ON(!irq_data);
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node = irq_data_get_node(irq_data);
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#ifdef CONFIG_X86_IO_APIC
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if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
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data = legacy_irq_data[virq + i];
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else
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#endif
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data = alloc_apic_chip_data(node);
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if (!data) {
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err = -ENOMEM;
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goto error;
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}
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irq_data->chip = &lapic_controller;
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irq_data->chip_data = data;
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irq_data->hwirq = virq + i;
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err = assign_irq_vector_policy(virq + i, node, data, info);
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if (err)
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goto error;
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}
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return 0;
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error:
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x86_vector_free_irqs(domain, virq, i + 1);
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return err;
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}
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static const struct irq_domain_ops x86_vector_domain_ops = {
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.alloc = x86_vector_alloc_irqs,
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.free = x86_vector_free_irqs,
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};
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int __init arch_probe_nr_irqs(void)
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{
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int nr;
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if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
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nr_irqs = NR_VECTORS * nr_cpu_ids;
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nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
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#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
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/*
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* for MSI and HT dyn irq
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*/
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if (gsi_top <= NR_IRQS_LEGACY)
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nr += 8 * nr_cpu_ids;
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else
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nr += gsi_top * 16;
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#endif
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if (nr < nr_irqs)
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nr_irqs = nr;
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|
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/*
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* We don't know if PIC is present at this point so we need to do
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* probe() to get the right number of legacy IRQs.
|
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*/
|
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return legacy_pic->probe();
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}
|
|
|
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#ifdef CONFIG_X86_IO_APIC
|
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static void init_legacy_irqs(void)
|
|
{
|
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int i, node = cpu_to_node(0);
|
|
struct apic_chip_data *data;
|
|
|
|
/*
|
|
* For legacy IRQ's, start with assigning irq0 to irq15 to
|
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* ISA_IRQ_VECTOR(i) for all cpu's.
|
|
*/
|
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for (i = 0; i < nr_legacy_irqs(); i++) {
|
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data = legacy_irq_data[i] = alloc_apic_chip_data(node);
|
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BUG_ON(!data);
|
|
|
|
data->cfg.vector = ISA_IRQ_VECTOR(i);
|
|
cpumask_setall(data->domain);
|
|
irq_set_chip_data(i, data);
|
|
}
|
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}
|
|
#else
|
|
static void init_legacy_irqs(void) { }
|
|
#endif
|
|
|
|
int __init arch_early_irq_init(void)
|
|
{
|
|
init_legacy_irqs();
|
|
|
|
x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
|
|
NULL);
|
|
BUG_ON(x86_vector_domain == NULL);
|
|
irq_set_default_host(x86_vector_domain);
|
|
|
|
arch_init_msi_domain(x86_vector_domain);
|
|
arch_init_htirq_domain(x86_vector_domain);
|
|
|
|
BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
|
|
BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
|
|
BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
|
|
|
|
return arch_early_ioapic_init();
|
|
}
|
|
|
|
/* Initialize vector_irq on a new cpu */
|
|
static void __setup_vector_irq(int cpu)
|
|
{
|
|
struct apic_chip_data *data;
|
|
struct irq_desc *desc;
|
|
int irq, vector;
|
|
|
|
/* Mark the inuse vectors */
|
|
for_each_irq_desc(irq, desc) {
|
|
struct irq_data *idata = irq_desc_get_irq_data(desc);
|
|
|
|
data = apic_chip_data(idata);
|
|
if (!data || !cpumask_test_cpu(cpu, data->domain))
|
|
continue;
|
|
vector = data->cfg.vector;
|
|
per_cpu(vector_irq, cpu)[vector] = desc;
|
|
}
|
|
/* Mark the free vectors */
|
|
for (vector = 0; vector < NR_VECTORS; ++vector) {
|
|
desc = per_cpu(vector_irq, cpu)[vector];
|
|
if (IS_ERR_OR_NULL(desc))
|
|
continue;
|
|
|
|
data = apic_chip_data(irq_desc_get_irq_data(desc));
|
|
if (!cpumask_test_cpu(cpu, data->domain))
|
|
per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Setup the vector to irq mappings. Must be called with vector_lock held.
|
|
*/
|
|
void setup_vector_irq(int cpu)
|
|
{
|
|
int irq;
|
|
|
|
lockdep_assert_held(&vector_lock);
|
|
/*
|
|
* On most of the platforms, legacy PIC delivers the interrupts on the
|
|
* boot cpu. But there are certain platforms where PIC interrupts are
|
|
* delivered to multiple cpu's. If the legacy IRQ is handled by the
|
|
* legacy PIC, for the new cpu that is coming online, setup the static
|
|
* legacy vector to irq mapping:
|
|
*/
|
|
for (irq = 0; irq < nr_legacy_irqs(); irq++)
|
|
per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
|
|
|
|
__setup_vector_irq(cpu);
|
|
}
|
|
|
|
static int apic_retrigger_irq(struct irq_data *irq_data)
|
|
{
|
|
struct apic_chip_data *data = apic_chip_data(irq_data);
|
|
unsigned long flags;
|
|
int cpu;
|
|
|
|
raw_spin_lock_irqsave(&vector_lock, flags);
|
|
cpu = cpumask_first_and(data->domain, cpu_online_mask);
|
|
apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
|
|
raw_spin_unlock_irqrestore(&vector_lock, flags);
|
|
|
|
return 1;
|
|
}
|
|
|
|
void apic_ack_edge(struct irq_data *data)
|
|
{
|
|
irq_complete_move(irqd_cfg(data));
|
|
irq_move_irq(data);
|
|
ack_APIC_irq();
|
|
}
|
|
|
|
static int apic_set_affinity(struct irq_data *irq_data,
|
|
const struct cpumask *dest, bool force)
|
|
{
|
|
struct apic_chip_data *data = irq_data->chip_data;
|
|
int err, irq = irq_data->irq;
|
|
|
|
if (!IS_ENABLED(CONFIG_SMP))
|
|
return -EPERM;
|
|
|
|
if (!cpumask_intersects(dest, cpu_online_mask))
|
|
return -EINVAL;
|
|
|
|
err = assign_irq_vector(irq, data, dest);
|
|
return err ? err : IRQ_SET_MASK_OK;
|
|
}
|
|
|
|
static struct irq_chip lapic_controller = {
|
|
.irq_ack = apic_ack_edge,
|
|
.irq_set_affinity = apic_set_affinity,
|
|
.irq_retrigger = apic_retrigger_irq,
|
|
};
|
|
|
|
#ifdef CONFIG_SMP
|
|
static void __send_cleanup_vector(struct apic_chip_data *data)
|
|
{
|
|
raw_spin_lock(&vector_lock);
|
|
cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
|
|
data->move_in_progress = 0;
|
|
if (!cpumask_empty(data->old_domain))
|
|
apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR);
|
|
raw_spin_unlock(&vector_lock);
|
|
}
|
|
|
|
void send_cleanup_vector(struct irq_cfg *cfg)
|
|
{
|
|
struct apic_chip_data *data;
|
|
|
|
data = container_of(cfg, struct apic_chip_data, cfg);
|
|
if (data->move_in_progress)
|
|
__send_cleanup_vector(data);
|
|
}
|
|
|
|
asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void)
|
|
{
|
|
unsigned vector, me;
|
|
|
|
entering_ack_irq();
|
|
|
|
/* Prevent vectors vanishing under us */
|
|
raw_spin_lock(&vector_lock);
|
|
|
|
me = smp_processor_id();
|
|
for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
|
|
struct apic_chip_data *data;
|
|
struct irq_desc *desc;
|
|
unsigned int irr;
|
|
|
|
retry:
|
|
desc = __this_cpu_read(vector_irq[vector]);
|
|
if (IS_ERR_OR_NULL(desc))
|
|
continue;
|
|
|
|
if (!raw_spin_trylock(&desc->lock)) {
|
|
raw_spin_unlock(&vector_lock);
|
|
cpu_relax();
|
|
raw_spin_lock(&vector_lock);
|
|
goto retry;
|
|
}
|
|
|
|
data = apic_chip_data(irq_desc_get_irq_data(desc));
|
|
if (!data)
|
|
goto unlock;
|
|
|
|
/*
|
|
* Nothing to cleanup if irq migration is in progress
|
|
* or this cpu is not set in the cleanup mask.
|
|
*/
|
|
if (data->move_in_progress ||
|
|
!cpumask_test_cpu(me, data->old_domain))
|
|
goto unlock;
|
|
|
|
/*
|
|
* We have two cases to handle here:
|
|
* 1) vector is unchanged but the target mask got reduced
|
|
* 2) vector and the target mask has changed
|
|
*
|
|
* #1 is obvious, but in #2 we have two vectors with the same
|
|
* irq descriptor: the old and the new vector. So we need to
|
|
* make sure that we only cleanup the old vector. The new
|
|
* vector has the current @vector number in the config and
|
|
* this cpu is part of the target mask. We better leave that
|
|
* one alone.
|
|
*/
|
|
if (vector == data->cfg.vector &&
|
|
cpumask_test_cpu(me, data->domain))
|
|
goto unlock;
|
|
|
|
irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
|
|
/*
|
|
* Check if the vector that needs to be cleanedup is
|
|
* registered at the cpu's IRR. If so, then this is not
|
|
* the best time to clean it up. Lets clean it up in the
|
|
* next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
|
|
* to myself.
|
|
*/
|
|
if (irr & (1 << (vector % 32))) {
|
|
apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
|
|
goto unlock;
|
|
}
|
|
__this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
|
|
cpumask_clear_cpu(me, data->old_domain);
|
|
unlock:
|
|
raw_spin_unlock(&desc->lock);
|
|
}
|
|
|
|
raw_spin_unlock(&vector_lock);
|
|
|
|
exiting_irq();
|
|
}
|
|
|
|
static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
|
|
{
|
|
unsigned me;
|
|
struct apic_chip_data *data;
|
|
|
|
data = container_of(cfg, struct apic_chip_data, cfg);
|
|
if (likely(!data->move_in_progress))
|
|
return;
|
|
|
|
me = smp_processor_id();
|
|
if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
|
|
__send_cleanup_vector(data);
|
|
}
|
|
|
|
void irq_complete_move(struct irq_cfg *cfg)
|
|
{
|
|
__irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
|
|
}
|
|
|
|
/*
|
|
* Called from fixup_irqs() with @desc->lock held and interrupts disabled.
|
|
*/
|
|
void irq_force_complete_move(struct irq_desc *desc)
|
|
{
|
|
struct irq_data *irqdata;
|
|
struct apic_chip_data *data;
|
|
struct irq_cfg *cfg;
|
|
unsigned int cpu;
|
|
|
|
/*
|
|
* The function is called for all descriptors regardless of which
|
|
* irqdomain they belong to. For example if an IRQ is provided by
|
|
* an irq_chip as part of a GPIO driver, the chip data for that
|
|
* descriptor is specific to the irq_chip in question.
|
|
*
|
|
* Check first that the chip_data is what we expect
|
|
* (apic_chip_data) before touching it any further.
|
|
*/
|
|
irqdata = irq_domain_get_irq_data(x86_vector_domain,
|
|
irq_desc_get_irq(desc));
|
|
if (!irqdata)
|
|
return;
|
|
|
|
data = apic_chip_data(irqdata);
|
|
cfg = data ? &data->cfg : NULL;
|
|
|
|
if (!cfg)
|
|
return;
|
|
|
|
/*
|
|
* This is tricky. If the cleanup of @data->old_domain has not been
|
|
* done yet, then the following setaffinity call will fail with
|
|
* -EBUSY. This can leave the interrupt in a stale state.
|
|
*
|
|
* All CPUs are stuck in stop machine with interrupts disabled so
|
|
* calling __irq_complete_move() would be completely pointless.
|
|
*/
|
|
raw_spin_lock(&vector_lock);
|
|
/*
|
|
* Clean out all offline cpus (including the outgoing one) from the
|
|
* old_domain mask.
|
|
*/
|
|
cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
|
|
|
|
/*
|
|
* If move_in_progress is cleared and the old_domain mask is empty,
|
|
* then there is nothing to cleanup. fixup_irqs() will take care of
|
|
* the stale vectors on the outgoing cpu.
|
|
*/
|
|
if (!data->move_in_progress && cpumask_empty(data->old_domain)) {
|
|
raw_spin_unlock(&vector_lock);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* 1) The interrupt is in move_in_progress state. That means that we
|
|
* have not seen an interrupt since the io_apic was reprogrammed to
|
|
* the new vector.
|
|
*
|
|
* 2) The interrupt has fired on the new vector, but the cleanup IPIs
|
|
* have not been processed yet.
|
|
*/
|
|
if (data->move_in_progress) {
|
|
/*
|
|
* In theory there is a race:
|
|
*
|
|
* set_ioapic(new_vector) <-- Interrupt is raised before update
|
|
* is effective, i.e. it's raised on
|
|
* the old vector.
|
|
*
|
|
* So if the target cpu cannot handle that interrupt before
|
|
* the old vector is cleaned up, we get a spurious interrupt
|
|
* and in the worst case the ioapic irq line becomes stale.
|
|
*
|
|
* But in case of cpu hotplug this should be a non issue
|
|
* because if the affinity update happens right before all
|
|
* cpus rendevouz in stop machine, there is no way that the
|
|
* interrupt can be blocked on the target cpu because all cpus
|
|
* loops first with interrupts enabled in stop machine, so the
|
|
* old vector is not yet cleaned up when the interrupt fires.
|
|
*
|
|
* So the only way to run into this issue is if the delivery
|
|
* of the interrupt on the apic/system bus would be delayed
|
|
* beyond the point where the target cpu disables interrupts
|
|
* in stop machine. I doubt that it can happen, but at least
|
|
* there is a theroretical chance. Virtualization might be
|
|
* able to expose this, but AFAICT the IOAPIC emulation is not
|
|
* as stupid as the real hardware.
|
|
*
|
|
* Anyway, there is nothing we can do about that at this point
|
|
* w/o refactoring the whole fixup_irq() business completely.
|
|
* We print at least the irq number and the old vector number,
|
|
* so we have the necessary information when a problem in that
|
|
* area arises.
|
|
*/
|
|
pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
|
|
irqdata->irq, cfg->old_vector);
|
|
}
|
|
/*
|
|
* If old_domain is not empty, then other cpus still have the irq
|
|
* descriptor set in their vector array. Clean it up.
|
|
*/
|
|
for_each_cpu(cpu, data->old_domain)
|
|
per_cpu(vector_irq, cpu)[cfg->old_vector] = VECTOR_UNUSED;
|
|
|
|
/* Cleanup the left overs of the (half finished) move */
|
|
cpumask_clear(data->old_domain);
|
|
data->move_in_progress = 0;
|
|
raw_spin_unlock(&vector_lock);
|
|
}
|
|
#endif
|
|
|
|
static void __init print_APIC_field(int base)
|
|
{
|
|
int i;
|
|
|
|
printk(KERN_DEBUG);
|
|
|
|
for (i = 0; i < 8; i++)
|
|
pr_cont("%08x", apic_read(base + i*0x10));
|
|
|
|
pr_cont("\n");
|
|
}
|
|
|
|
static void __init print_local_APIC(void *dummy)
|
|
{
|
|
unsigned int i, v, ver, maxlvt;
|
|
u64 icr;
|
|
|
|
pr_debug("printing local APIC contents on CPU#%d/%d:\n",
|
|
smp_processor_id(), hard_smp_processor_id());
|
|
v = apic_read(APIC_ID);
|
|
pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
|
|
v = apic_read(APIC_LVR);
|
|
pr_info("... APIC VERSION: %08x\n", v);
|
|
ver = GET_APIC_VERSION(v);
|
|
maxlvt = lapic_get_maxlvt();
|
|
|
|
v = apic_read(APIC_TASKPRI);
|
|
pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
|
|
|
|
/* !82489DX */
|
|
if (APIC_INTEGRATED(ver)) {
|
|
if (!APIC_XAPIC(ver)) {
|
|
v = apic_read(APIC_ARBPRI);
|
|
pr_debug("... APIC ARBPRI: %08x (%02x)\n",
|
|
v, v & APIC_ARBPRI_MASK);
|
|
}
|
|
v = apic_read(APIC_PROCPRI);
|
|
pr_debug("... APIC PROCPRI: %08x\n", v);
|
|
}
|
|
|
|
/*
|
|
* Remote read supported only in the 82489DX and local APIC for
|
|
* Pentium processors.
|
|
*/
|
|
if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
|
|
v = apic_read(APIC_RRR);
|
|
pr_debug("... APIC RRR: %08x\n", v);
|
|
}
|
|
|
|
v = apic_read(APIC_LDR);
|
|
pr_debug("... APIC LDR: %08x\n", v);
|
|
if (!x2apic_enabled()) {
|
|
v = apic_read(APIC_DFR);
|
|
pr_debug("... APIC DFR: %08x\n", v);
|
|
}
|
|
v = apic_read(APIC_SPIV);
|
|
pr_debug("... APIC SPIV: %08x\n", v);
|
|
|
|
pr_debug("... APIC ISR field:\n");
|
|
print_APIC_field(APIC_ISR);
|
|
pr_debug("... APIC TMR field:\n");
|
|
print_APIC_field(APIC_TMR);
|
|
pr_debug("... APIC IRR field:\n");
|
|
print_APIC_field(APIC_IRR);
|
|
|
|
/* !82489DX */
|
|
if (APIC_INTEGRATED(ver)) {
|
|
/* Due to the Pentium erratum 3AP. */
|
|
if (maxlvt > 3)
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
v = apic_read(APIC_ESR);
|
|
pr_debug("... APIC ESR: %08x\n", v);
|
|
}
|
|
|
|
icr = apic_icr_read();
|
|
pr_debug("... APIC ICR: %08x\n", (u32)icr);
|
|
pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
|
|
|
|
v = apic_read(APIC_LVTT);
|
|
pr_debug("... APIC LVTT: %08x\n", v);
|
|
|
|
if (maxlvt > 3) {
|
|
/* PC is LVT#4. */
|
|
v = apic_read(APIC_LVTPC);
|
|
pr_debug("... APIC LVTPC: %08x\n", v);
|
|
}
|
|
v = apic_read(APIC_LVT0);
|
|
pr_debug("... APIC LVT0: %08x\n", v);
|
|
v = apic_read(APIC_LVT1);
|
|
pr_debug("... APIC LVT1: %08x\n", v);
|
|
|
|
if (maxlvt > 2) {
|
|
/* ERR is LVT#3. */
|
|
v = apic_read(APIC_LVTERR);
|
|
pr_debug("... APIC LVTERR: %08x\n", v);
|
|
}
|
|
|
|
v = apic_read(APIC_TMICT);
|
|
pr_debug("... APIC TMICT: %08x\n", v);
|
|
v = apic_read(APIC_TMCCT);
|
|
pr_debug("... APIC TMCCT: %08x\n", v);
|
|
v = apic_read(APIC_TDCR);
|
|
pr_debug("... APIC TDCR: %08x\n", v);
|
|
|
|
if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
|
|
v = apic_read(APIC_EFEAT);
|
|
maxlvt = (v >> 16) & 0xff;
|
|
pr_debug("... APIC EFEAT: %08x\n", v);
|
|
v = apic_read(APIC_ECTRL);
|
|
pr_debug("... APIC ECTRL: %08x\n", v);
|
|
for (i = 0; i < maxlvt; i++) {
|
|
v = apic_read(APIC_EILVTn(i));
|
|
pr_debug("... APIC EILVT%d: %08x\n", i, v);
|
|
}
|
|
}
|
|
pr_cont("\n");
|
|
}
|
|
|
|
static void __init print_local_APICs(int maxcpu)
|
|
{
|
|
int cpu;
|
|
|
|
if (!maxcpu)
|
|
return;
|
|
|
|
preempt_disable();
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu >= maxcpu)
|
|
break;
|
|
smp_call_function_single(cpu, print_local_APIC, NULL, 1);
|
|
}
|
|
preempt_enable();
|
|
}
|
|
|
|
static void __init print_PIC(void)
|
|
{
|
|
unsigned int v;
|
|
unsigned long flags;
|
|
|
|
if (!nr_legacy_irqs())
|
|
return;
|
|
|
|
pr_debug("\nprinting PIC contents\n");
|
|
|
|
raw_spin_lock_irqsave(&i8259A_lock, flags);
|
|
|
|
v = inb(0xa1) << 8 | inb(0x21);
|
|
pr_debug("... PIC IMR: %04x\n", v);
|
|
|
|
v = inb(0xa0) << 8 | inb(0x20);
|
|
pr_debug("... PIC IRR: %04x\n", v);
|
|
|
|
outb(0x0b, 0xa0);
|
|
outb(0x0b, 0x20);
|
|
v = inb(0xa0) << 8 | inb(0x20);
|
|
outb(0x0a, 0xa0);
|
|
outb(0x0a, 0x20);
|
|
|
|
raw_spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
|
|
pr_debug("... PIC ISR: %04x\n", v);
|
|
|
|
v = inb(0x4d1) << 8 | inb(0x4d0);
|
|
pr_debug("... PIC ELCR: %04x\n", v);
|
|
}
|
|
|
|
static int show_lapic __initdata = 1;
|
|
static __init int setup_show_lapic(char *arg)
|
|
{
|
|
int num = -1;
|
|
|
|
if (strcmp(arg, "all") == 0) {
|
|
show_lapic = CONFIG_NR_CPUS;
|
|
} else {
|
|
get_option(&arg, &num);
|
|
if (num >= 0)
|
|
show_lapic = num;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
__setup("show_lapic=", setup_show_lapic);
|
|
|
|
static int __init print_ICs(void)
|
|
{
|
|
if (apic_verbosity == APIC_QUIET)
|
|
return 0;
|
|
|
|
print_PIC();
|
|
|
|
/* don't print out if apic is not there */
|
|
if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
|
|
return 0;
|
|
|
|
print_local_APICs(show_lapic);
|
|
print_IO_APICs();
|
|
|
|
return 0;
|
|
}
|
|
|
|
late_initcall(print_ICs);
|