Joseph Greathouse 18c6b74e7c drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus ... In previous gfx9 parts, S_BARRIER shader instructions are implicitly S_WAITCNT 0 instructions as well. This setting turns off that mechanism in Arcturus and beyond. With this, shaders must follow the ISA guide insofar as putting in explicit S_WAITCNT operations even after an S_BARRIER. v2: Fix patch title to list component Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-01-30 17:15:27 -05:00
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gc_9_0_default.h	drm/amdgpu: remove some old gc 9.x registers	2017-12-13 17:28:08 -05:00
gc_9_0_offset.h	drm/amdgpu: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support Arcturus	2019-12-23 14:56:37 -05:00
gc_9_0_sh_mask.h	drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus	2020-01-30 17:15:27 -05:00
gc_9_1_offset.h	drm/amdgpu: remove some old gc 9.x registers	2017-12-13 17:28:08 -05:00
gc_9_1_sh_mask.h	drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header files	2018-03-07 16:10:13 -05:00
gc_9_2_1_offset.h	drm/amd/include: Add ip header files for vega12.	2018-03-21 14:23:01 -05:00
gc_9_2_1_sh_mask.h	drm/amd/include: update the bitfield define for PF_MAX_REGION	2018-09-10 22:45:51 -05:00
gc_9_4_1_offset.h	drm/amdgpu: add EDC counter registers of gc for Arcturus	2020-01-22 16:36:22 -05:00
gc_9_4_1_sh_mask.h	drm/amdgpu: add EDC counter registers of gc for Arcturus	2020-01-22 16:36:22 -05:00
gc_10_1_0_default.h	drm/amdgpu: add GC 10.1 register headers (v4)	2019-06-20 15:54:35 -05:00
gc_10_1_0_offset.h	drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc header	2019-08-02 10:30:40 -05:00
gc_10_1_0_sh_mask.h	drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc header	2019-08-02 10:30:40 -05:00