forked from Minki/linux
7ac0f700a6
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that boards that share the same pinctrl setting do not have to define it time and time again in <board>.dts. However, along with the devices and use cases being added continuously, the pinctrl setting nodes under iomuxc becomes more than expected. This bloats device tree blob for particular board unnecessarily since only a small subset of those pinctrl setting nodes will be used by the board. It impacts not only the DTB file size but also the run-time device tree lookup efficiency. The patch moves all the pinctrl data into individual boards as needed. With the changes, the pinctrl setting nodes becomes local to particular board, and it makes no sense to continue numbering the setting for given peripheral. Thus, all the pinctrl phandler name gets updated to have only peripheral name in there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
190 lines
4.2 KiB
Plaintext
190 lines
4.2 KiB
Plaintext
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx53.dtsi"
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/ {
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model = "Freescale i.MX53 Evaluation Kit";
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compatible = "fsl,imx53-evk", "fsl,imx53";
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memory {
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reg = <0x70000000 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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green {
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label = "Heartbeat";
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gpios = <&gpio7 7 0>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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cd-gpios = <&gpio3 13 0>;
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wp-gpios = <&gpio3 14 0>;
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status = "okay";
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
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status = "okay";
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flash: at45db321d@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
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spi-max-frequency = <25000000>;
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reg = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x40000>;
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read-only;
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};
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partition@40000 {
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label = "Kernel";
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reg = <0x40000 0x3c0000>;
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};
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};
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};
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&esdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc3>;
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cd-gpios = <&gpio3 11 0>;
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wp-gpios = <&gpio3 12 0>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx53-evk {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
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MX53_PAD_EIM_D19__GPIO3_19 0x80000000
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MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
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MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
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MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
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MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
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MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
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MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
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MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
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MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
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>;
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};
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
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MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
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MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
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MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
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MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
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MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
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>;
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};
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pinctrl_esdhc3: esdhc3grp {
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fsl,pins = <
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MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
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MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
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MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
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MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
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MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
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MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
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MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
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MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
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MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
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MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
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MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
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MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
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>;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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pmic: mc13892@08 {
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compatible = "fsl,mc13892", "fsl,mc13xxx";
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reg = <0x08>;
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};
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codec: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio7 6 0>;
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status = "okay";
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};
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