forked from Minki/linux
5a2a7d57ee
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that boards that share the same pinctrl setting do not have to define it time and time again in <board>.dts. However, along with the devices and use cases being added continuously, the pinctrl setting nodes under iomuxc becomes more than expected. This bloats device tree blob for particular board unnecessarily since only a small subset of those pinctrl setting nodes will be used by the board. It impacts not only the DTB file size but also the run-time device tree lookup efficiency. The patch moves all the pinctrl data into individual boards as needed. With the changes, the pinctrl setting nodes becomes local to particular board, and it makes no sense to continue numbering the setting for given peripheral. Thus, all the pinctrl phandler name gets updated to have only peripheral name in there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
90 lines
2.1 KiB
Plaintext
90 lines
2.1 KiB
Plaintext
/*
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* Copyright 2012 Armadeus Systems - <support@armadeus.com>
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* Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
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*
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* Based on mx51-babbage.dts
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx51.dtsi"
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/ {
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model = "Armadeus Systems APF51 module";
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compatible = "armadeus,imx51-apf51", "fsl,imx51";
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memory {
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reg = <0x90000000 0x20000000>;
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};
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clocks {
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osc {
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clock-frequency = <33554432>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "mii";
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phy-reset-gpios = <&gpio3 0 0>;
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phy-reset-duration = <1>;
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status = "okay";
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};
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&iomuxc {
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imx51-apf51 {
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
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MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
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MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
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MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
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MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
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MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
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MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
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MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
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MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
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MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
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MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
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MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
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MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
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MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
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MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
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MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
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MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
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MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
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MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
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>;
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};
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};
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};
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&nfc {
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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