Anup Patel 196a14d451 RISC-V: Use tabs to align macro values in asm/csr.h ... The spacing between macro name and value is not consistent in asm/csr.h. This patch beautifies asm/csr.h by using tabs to align macro values instead of spaces. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-05-16 20:42:11 -07:00
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boot	RISC-V: Build flat and compressed kernel images	2018-11-20 05:19:09 -08:00
configs	RISC-V: Add separate defconfig for 32bit systems	2019-04-09 09:42:49 -07:00
include	RISC-V: Use tabs to align macro values in asm/csr.h	2019-05-16 20:42:11 -07:00
kernel	RISC-V: Fix minor checkpatch issues.	2019-05-16 20:42:11 -07:00
lib	RISC-V: lib: minor asm cleanup	2018-12-21 08:17:02 -08:00
mm	RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems	2019-04-10 09:41:40 -07:00
net	bpf, riscv: add BPF JIT for RV64G	2019-02-05 16:56:10 +01:00
Kconfig	riscv: remove CONFIG_RISCV_ISA_A	2019-04-25 14:51:10 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Makefile	riscv: remove CONFIG_RISCV_ISA_A	2019-04-25 14:51:10 -07:00