forked from Minki/linux
18743d2781
Now that the GIC properly uses IRQ domains, kill off the per-platform routing tables that were used to make the GIC appear transparent. This includes: - removing the mapping tables and the support for applying them, - moving GIC IPI support to the GIC driver, - properly routing the i8259 through the GIC on Malta, and - updating IRQ assignments on SEAD-3 when the GIC is present. Platforms no longer will pass an interrupt mapping table to gic_init. Instead, they will pass the CPU interrupt vector (2 - 7) that they expect the GIC to route interrupts to. Note that in EIC mode this value is ignored and all GIC interrupts are routed to EIC vector 1. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7816/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
31 lines
804 B
C
31 lines
804 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
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* Douglas Leung <douglas@mips.com>
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* Steven J. Hill <sjhill@mips.com>
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*/
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#ifndef _MIPS_SEAD3INT_H
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#define _MIPS_SEAD3INT_H
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/* SEAD-3 GIC address space definitions. */
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#define GIC_BASE_ADDR 0x1b1c0000
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#define GIC_ADDRSPACE_SZ (128 * 1024)
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/* CPU interrupt offsets */
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#define CPU_INT_GIC 2
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#define CPU_INT_EHCI 2
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#define CPU_INT_UART0 4
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#define CPU_INT_UART1 4
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#define CPU_INT_NET 6
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/* GIC interrupt offsets */
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#define GIC_INT_NET 0
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#define GIC_INT_UART1 2
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#define GIC_INT_UART0 3
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#define GIC_INT_EHCI 5
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#endif /* !(_MIPS_SEAD3INT_H) */
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