Rohit Khaire 18703923a6 drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid ... RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different offsets for Sienna Cichlid Signed-off-by: Rohit Khaire <rohit.khaire@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-06-04 16:02:44 -04:00
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acp
amdgpu	drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid	2021-06-04 16:02:44 -04:00
amdkfd	drm/amdkfd: Make TLB flush conditional on mapping	2021-06-04 12:40:01 -04:00
display	drm/amd/display: Keep linebuffer pixel depth at 30bpp for DCE-11.0.	2021-06-04 12:40:01 -04:00
include	drm/amd/pm: sysfs attrs to read ss powershare (v6)	2021-06-04 12:40:00 -04:00
pm	drm/amd/pm: Use generic BACO function for smu11 ASICs	2021-06-04 16:02:33 -04:00