forked from Minki/linux
5436 lines
192 KiB
C
5436 lines
192 KiB
C
#ifndef A6XX_XML
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#define A6XX_XML
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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Copyright (C) 2013-2018 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum a6xx_color_fmt {
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RB6_A8_UNORM = 2,
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RB6_R8_UNORM = 3,
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RB6_R8_SNORM = 4,
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RB6_R8_UINT = 5,
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RB6_R8_SINT = 6,
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RB6_R4G4B4A4_UNORM = 8,
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RB6_R5G5B5A1_UNORM = 10,
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RB6_R5G6B5_UNORM = 14,
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RB6_R8G8_UNORM = 15,
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RB6_R8G8_SNORM = 16,
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RB6_R8G8_UINT = 17,
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RB6_R8G8_SINT = 18,
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RB6_R16_UNORM = 21,
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RB6_R16_SNORM = 22,
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RB6_R16_FLOAT = 23,
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RB6_R16_UINT = 24,
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RB6_R16_SINT = 25,
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RB6_R8G8B8A8_UNORM = 48,
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RB6_R8G8B8_UNORM = 49,
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RB6_R8G8B8A8_SNORM = 50,
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RB6_R8G8B8A8_UINT = 51,
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RB6_R8G8B8A8_SINT = 52,
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RB6_R10G10B10A2_UNORM = 55,
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RB6_R10G10B10A2_UINT = 58,
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RB6_R11G11B10_FLOAT = 66,
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RB6_R16G16_UNORM = 67,
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RB6_R16G16_SNORM = 68,
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RB6_R16G16_FLOAT = 69,
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RB6_R16G16_UINT = 70,
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RB6_R16G16_SINT = 71,
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RB6_R32_FLOAT = 74,
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RB6_R32_UINT = 75,
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RB6_R32_SINT = 76,
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RB6_R16G16B16A16_UNORM = 96,
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RB6_R16G16B16A16_SNORM = 97,
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RB6_R16G16B16A16_FLOAT = 98,
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RB6_R16G16B16A16_UINT = 99,
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RB6_R16G16B16A16_SINT = 100,
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RB6_R32G32_FLOAT = 103,
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RB6_R32G32_UINT = 104,
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RB6_R32G32_SINT = 105,
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RB6_R32G32B32A32_FLOAT = 130,
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RB6_R32G32B32A32_UINT = 131,
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RB6_R32G32B32A32_SINT = 132,
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RB6_X8Z24_UNORM = 160,
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};
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enum a6xx_tile_mode {
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TILE6_LINEAR = 0,
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TILE6_2 = 2,
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TILE6_3 = 3,
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};
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enum a6xx_vtx_fmt {
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VFMT6_8_UNORM = 3,
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VFMT6_8_SNORM = 4,
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VFMT6_8_UINT = 5,
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VFMT6_8_SINT = 6,
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VFMT6_8_8_UNORM = 15,
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VFMT6_8_8_SNORM = 16,
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VFMT6_8_8_UINT = 17,
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VFMT6_8_8_SINT = 18,
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VFMT6_16_UNORM = 21,
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VFMT6_16_SNORM = 22,
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VFMT6_16_FLOAT = 23,
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VFMT6_16_UINT = 24,
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VFMT6_16_SINT = 25,
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VFMT6_8_8_8_UNORM = 33,
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VFMT6_8_8_8_SNORM = 34,
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VFMT6_8_8_8_UINT = 35,
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VFMT6_8_8_8_SINT = 36,
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VFMT6_8_8_8_8_UNORM = 48,
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VFMT6_8_8_8_8_SNORM = 50,
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VFMT6_8_8_8_8_UINT = 51,
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VFMT6_8_8_8_8_SINT = 52,
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VFMT6_10_10_10_2_UNORM = 54,
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VFMT6_10_10_10_2_SNORM = 57,
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VFMT6_10_10_10_2_UINT = 58,
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VFMT6_10_10_10_2_SINT = 59,
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VFMT6_11_11_10_FLOAT = 66,
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VFMT6_16_16_UNORM = 67,
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VFMT6_16_16_SNORM = 68,
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VFMT6_16_16_FLOAT = 69,
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VFMT6_16_16_UINT = 70,
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VFMT6_16_16_SINT = 71,
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VFMT6_32_UNORM = 72,
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VFMT6_32_SNORM = 73,
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VFMT6_32_FLOAT = 74,
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VFMT6_32_UINT = 75,
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VFMT6_32_SINT = 76,
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VFMT6_32_FIXED = 77,
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VFMT6_16_16_16_UNORM = 88,
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VFMT6_16_16_16_SNORM = 89,
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VFMT6_16_16_16_FLOAT = 90,
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VFMT6_16_16_16_UINT = 91,
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VFMT6_16_16_16_SINT = 92,
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VFMT6_16_16_16_16_UNORM = 96,
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VFMT6_16_16_16_16_SNORM = 97,
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VFMT6_16_16_16_16_FLOAT = 98,
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VFMT6_16_16_16_16_UINT = 99,
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VFMT6_16_16_16_16_SINT = 100,
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VFMT6_32_32_UNORM = 101,
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VFMT6_32_32_SNORM = 102,
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VFMT6_32_32_FLOAT = 103,
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VFMT6_32_32_UINT = 104,
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VFMT6_32_32_SINT = 105,
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VFMT6_32_32_FIXED = 106,
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VFMT6_32_32_32_UNORM = 112,
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VFMT6_32_32_32_SNORM = 113,
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VFMT6_32_32_32_UINT = 114,
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VFMT6_32_32_32_SINT = 115,
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VFMT6_32_32_32_FLOAT = 116,
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VFMT6_32_32_32_FIXED = 117,
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VFMT6_32_32_32_32_UNORM = 128,
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VFMT6_32_32_32_32_SNORM = 129,
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VFMT6_32_32_32_32_FLOAT = 130,
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VFMT6_32_32_32_32_UINT = 131,
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VFMT6_32_32_32_32_SINT = 132,
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VFMT6_32_32_32_32_FIXED = 133,
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};
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enum a6xx_tex_fmt {
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TFMT6_A8_UNORM = 2,
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TFMT6_8_UNORM = 3,
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TFMT6_8_SNORM = 4,
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TFMT6_8_UINT = 5,
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TFMT6_8_SINT = 6,
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TFMT6_4_4_4_4_UNORM = 8,
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TFMT6_5_5_5_1_UNORM = 10,
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TFMT6_5_6_5_UNORM = 14,
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TFMT6_8_8_UNORM = 15,
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TFMT6_8_8_SNORM = 16,
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TFMT6_8_8_UINT = 17,
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TFMT6_8_8_SINT = 18,
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TFMT6_L8_A8_UNORM = 19,
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TFMT6_16_UNORM = 21,
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TFMT6_16_SNORM = 22,
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TFMT6_16_FLOAT = 23,
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TFMT6_16_UINT = 24,
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TFMT6_16_SINT = 25,
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TFMT6_8_8_8_8_UNORM = 48,
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TFMT6_8_8_8_UNORM = 49,
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TFMT6_8_8_8_8_SNORM = 50,
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TFMT6_8_8_8_8_UINT = 51,
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TFMT6_8_8_8_8_SINT = 52,
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TFMT6_9_9_9_E5_FLOAT = 53,
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TFMT6_10_10_10_2_UNORM = 54,
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TFMT6_10_10_10_2_UINT = 58,
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TFMT6_11_11_10_FLOAT = 66,
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TFMT6_16_16_UNORM = 67,
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TFMT6_16_16_SNORM = 68,
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TFMT6_16_16_FLOAT = 69,
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TFMT6_16_16_UINT = 70,
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TFMT6_16_16_SINT = 71,
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TFMT6_32_FLOAT = 74,
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TFMT6_32_UINT = 75,
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TFMT6_32_SINT = 76,
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TFMT6_16_16_16_16_UNORM = 96,
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TFMT6_16_16_16_16_SNORM = 97,
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TFMT6_16_16_16_16_FLOAT = 98,
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TFMT6_16_16_16_16_UINT = 99,
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TFMT6_16_16_16_16_SINT = 100,
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TFMT6_32_32_FLOAT = 103,
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TFMT6_32_32_UINT = 104,
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TFMT6_32_32_SINT = 105,
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TFMT6_32_32_32_UINT = 114,
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TFMT6_32_32_32_SINT = 115,
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TFMT6_32_32_32_FLOAT = 116,
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TFMT6_32_32_32_32_FLOAT = 130,
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TFMT6_32_32_32_32_UINT = 131,
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TFMT6_32_32_32_32_SINT = 132,
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TFMT6_X8Z24_UNORM = 160,
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TFMT6_ETC2_RG11_UNORM = 171,
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TFMT6_ETC2_RG11_SNORM = 172,
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TFMT6_ETC2_R11_UNORM = 173,
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TFMT6_ETC2_R11_SNORM = 174,
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TFMT6_ETC1 = 175,
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TFMT6_ETC2_RGB8 = 176,
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TFMT6_ETC2_RGBA8 = 177,
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TFMT6_ETC2_RGB8A1 = 178,
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TFMT6_DXT1 = 179,
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TFMT6_DXT3 = 180,
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TFMT6_DXT5 = 181,
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TFMT6_RGTC1_UNORM = 183,
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TFMT6_RGTC1_SNORM = 184,
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TFMT6_RGTC2_UNORM = 187,
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TFMT6_RGTC2_SNORM = 188,
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TFMT6_BPTC_UFLOAT = 190,
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TFMT6_BPTC_FLOAT = 191,
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TFMT6_BPTC = 192,
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TFMT6_ASTC_4x4 = 193,
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TFMT6_ASTC_5x4 = 194,
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TFMT6_ASTC_5x5 = 195,
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TFMT6_ASTC_6x5 = 196,
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TFMT6_ASTC_6x6 = 197,
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TFMT6_ASTC_8x5 = 198,
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TFMT6_ASTC_8x6 = 199,
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TFMT6_ASTC_8x8 = 200,
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TFMT6_ASTC_10x5 = 201,
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TFMT6_ASTC_10x6 = 202,
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TFMT6_ASTC_10x8 = 203,
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TFMT6_ASTC_10x10 = 204,
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TFMT6_ASTC_12x10 = 205,
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TFMT6_ASTC_12x12 = 206,
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};
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enum a6xx_tex_fetchsize {
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TFETCH6_1_BYTE = 0,
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TFETCH6_2_BYTE = 1,
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TFETCH6_4_BYTE = 2,
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TFETCH6_8_BYTE = 3,
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TFETCH6_16_BYTE = 4,
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};
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enum a6xx_depth_format {
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DEPTH6_NONE = 0,
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DEPTH6_16 = 1,
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DEPTH6_24_8 = 2,
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DEPTH6_32 = 4,
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};
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enum a6xx_shader_id {
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A6XX_TP0_TMO_DATA = 9,
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A6XX_TP0_SMO_DATA = 10,
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A6XX_TP0_MIPMAP_BASE_DATA = 11,
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A6XX_TP1_TMO_DATA = 25,
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A6XX_TP1_SMO_DATA = 26,
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A6XX_TP1_MIPMAP_BASE_DATA = 27,
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A6XX_SP_INST_DATA = 41,
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A6XX_SP_LB_0_DATA = 42,
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A6XX_SP_LB_1_DATA = 43,
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A6XX_SP_LB_2_DATA = 44,
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A6XX_SP_LB_3_DATA = 45,
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A6XX_SP_LB_4_DATA = 46,
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A6XX_SP_LB_5_DATA = 47,
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A6XX_SP_CB_BINDLESS_DATA = 48,
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A6XX_SP_CB_LEGACY_DATA = 49,
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A6XX_SP_UAV_DATA = 50,
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A6XX_SP_INST_TAG = 51,
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A6XX_SP_CB_BINDLESS_TAG = 52,
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A6XX_SP_TMO_UMO_TAG = 53,
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A6XX_SP_SMO_TAG = 54,
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A6XX_SP_STATE_DATA = 55,
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A6XX_HLSQ_CHUNK_CVS_RAM = 73,
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A6XX_HLSQ_CHUNK_CPS_RAM = 74,
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A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
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A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
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A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
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A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
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A6XX_HLSQ_CVS_MISC_RAM = 80,
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A6XX_HLSQ_CPS_MISC_RAM = 81,
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A6XX_HLSQ_INST_RAM = 82,
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A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
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A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
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A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
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A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
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A6XX_HLSQ_INST_RAM_TAG = 87,
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A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
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A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
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A6XX_HLSQ_PWR_REST_RAM = 90,
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A6XX_HLSQ_PWR_REST_TAG = 91,
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A6XX_HLSQ_DATAPATH_META = 96,
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A6XX_HLSQ_FRONTEND_META = 97,
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A6XX_HLSQ_INDIRECT_META = 98,
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A6XX_HLSQ_BACKEND_META = 99,
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};
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enum a6xx_debugbus_id {
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A6XX_DBGBUS_CP = 1,
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A6XX_DBGBUS_RBBM = 2,
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A6XX_DBGBUS_VBIF = 3,
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A6XX_DBGBUS_HLSQ = 4,
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A6XX_DBGBUS_UCHE = 5,
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A6XX_DBGBUS_DPM = 6,
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A6XX_DBGBUS_TESS = 7,
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A6XX_DBGBUS_PC = 8,
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A6XX_DBGBUS_VFDP = 9,
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A6XX_DBGBUS_VPC = 10,
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A6XX_DBGBUS_TSE = 11,
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A6XX_DBGBUS_RAS = 12,
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A6XX_DBGBUS_VSC = 13,
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A6XX_DBGBUS_COM = 14,
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A6XX_DBGBUS_LRZ = 16,
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A6XX_DBGBUS_A2D = 17,
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A6XX_DBGBUS_CCUFCHE = 18,
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A6XX_DBGBUS_GMU_CX = 19,
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A6XX_DBGBUS_RBP = 20,
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A6XX_DBGBUS_DCS = 21,
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A6XX_DBGBUS_DBGC = 22,
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A6XX_DBGBUS_CX = 23,
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A6XX_DBGBUS_GMU_GX = 24,
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A6XX_DBGBUS_TPFCHE = 25,
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A6XX_DBGBUS_GBIF_GX = 26,
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A6XX_DBGBUS_GPC = 29,
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A6XX_DBGBUS_LARC = 30,
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A6XX_DBGBUS_HLSQ_SPTP = 31,
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A6XX_DBGBUS_RB_0 = 32,
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A6XX_DBGBUS_RB_1 = 33,
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A6XX_DBGBUS_UCHE_WRAPPER = 36,
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A6XX_DBGBUS_CCU_0 = 40,
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A6XX_DBGBUS_CCU_1 = 41,
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A6XX_DBGBUS_VFD_0 = 56,
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A6XX_DBGBUS_VFD_1 = 57,
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A6XX_DBGBUS_VFD_2 = 58,
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A6XX_DBGBUS_VFD_3 = 59,
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A6XX_DBGBUS_SP_0 = 64,
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A6XX_DBGBUS_SP_1 = 65,
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A6XX_DBGBUS_TPL1_0 = 72,
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A6XX_DBGBUS_TPL1_1 = 73,
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A6XX_DBGBUS_TPL1_2 = 74,
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A6XX_DBGBUS_TPL1_3 = 75,
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};
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enum a6xx_cp_perfcounter_select {
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PERF_CP_ALWAYS_COUNT = 0,
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PERF_CP_BUSY_GFX_CORE_IDLE = 1,
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PERF_CP_BUSY_CYCLES = 2,
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PERF_CP_NUM_PREEMPTIONS = 3,
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PERF_CP_PREEMPTION_REACTION_DELAY = 4,
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PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
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PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
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PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
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PERF_CP_PREDICATED_DRAWS_KILLED = 8,
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PERF_CP_MODE_SWITCH = 9,
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PERF_CP_ZPASS_DONE = 10,
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PERF_CP_CONTEXT_DONE = 11,
|
|
PERF_CP_CACHE_FLUSH = 12,
|
|
PERF_CP_LONG_PREEMPTIONS = 13,
|
|
PERF_CP_SQE_I_CACHE_STARVE = 14,
|
|
PERF_CP_SQE_IDLE = 15,
|
|
PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
|
|
PERF_CP_SQE_PM4_STARVE_SDS = 17,
|
|
PERF_CP_SQE_MRB_STARVE = 18,
|
|
PERF_CP_SQE_RRB_STARVE = 19,
|
|
PERF_CP_SQE_VSD_STARVE = 20,
|
|
PERF_CP_VSD_DECODE_STARVE = 21,
|
|
PERF_CP_SQE_PIPE_OUT_STALL = 22,
|
|
PERF_CP_SQE_SYNC_STALL = 23,
|
|
PERF_CP_SQE_PM4_WFI_STALL = 24,
|
|
PERF_CP_SQE_SYS_WFI_STALL = 25,
|
|
PERF_CP_SQE_T4_EXEC = 26,
|
|
PERF_CP_SQE_LOAD_STATE_EXEC = 27,
|
|
PERF_CP_SQE_SAVE_SDS_STATE = 28,
|
|
PERF_CP_SQE_DRAW_EXEC = 29,
|
|
PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
|
|
PERF_CP_SQE_EXEC_PROFILED = 31,
|
|
PERF_CP_MEMORY_POOL_EMPTY = 32,
|
|
PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
|
|
PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
|
|
PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
|
|
PERF_CP_AHB_STALL_SQE_GMU = 36,
|
|
PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
|
|
PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
|
|
PERF_CP_CLUSTER0_EMPTY = 39,
|
|
PERF_CP_CLUSTER1_EMPTY = 40,
|
|
PERF_CP_CLUSTER2_EMPTY = 41,
|
|
PERF_CP_CLUSTER3_EMPTY = 42,
|
|
PERF_CP_CLUSTER4_EMPTY = 43,
|
|
PERF_CP_CLUSTER5_EMPTY = 44,
|
|
PERF_CP_PM4_DATA = 45,
|
|
PERF_CP_PM4_HEADERS = 46,
|
|
PERF_CP_VBIF_READ_BEATS = 47,
|
|
PERF_CP_VBIF_WRITE_BEATS = 48,
|
|
PERF_CP_SQE_INSTR_COUNTER = 49,
|
|
};
|
|
|
|
enum a6xx_rbbm_perfcounter_select {
|
|
PERF_RBBM_ALWAYS_COUNT = 0,
|
|
PERF_RBBM_ALWAYS_ON = 1,
|
|
PERF_RBBM_TSE_BUSY = 2,
|
|
PERF_RBBM_RAS_BUSY = 3,
|
|
PERF_RBBM_PC_DCALL_BUSY = 4,
|
|
PERF_RBBM_PC_VSD_BUSY = 5,
|
|
PERF_RBBM_STATUS_MASKED = 6,
|
|
PERF_RBBM_COM_BUSY = 7,
|
|
PERF_RBBM_DCOM_BUSY = 8,
|
|
PERF_RBBM_VBIF_BUSY = 9,
|
|
PERF_RBBM_VSC_BUSY = 10,
|
|
PERF_RBBM_TESS_BUSY = 11,
|
|
PERF_RBBM_UCHE_BUSY = 12,
|
|
PERF_RBBM_HLSQ_BUSY = 13,
|
|
};
|
|
|
|
enum a6xx_pc_perfcounter_select {
|
|
PERF_PC_BUSY_CYCLES = 0,
|
|
PERF_PC_WORKING_CYCLES = 1,
|
|
PERF_PC_STALL_CYCLES_VFD = 2,
|
|
PERF_PC_STALL_CYCLES_TSE = 3,
|
|
PERF_PC_STALL_CYCLES_VPC = 4,
|
|
PERF_PC_STALL_CYCLES_UCHE = 5,
|
|
PERF_PC_STALL_CYCLES_TESS = 6,
|
|
PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
|
|
PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
|
|
PERF_PC_PASS1_TF_STALL_CYCLES = 9,
|
|
PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
|
|
PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
|
|
PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
|
|
PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
|
|
PERF_PC_STARVE_CYCLES_DI = 14,
|
|
PERF_PC_VIS_STREAMS_LOADED = 15,
|
|
PERF_PC_INSTANCES = 16,
|
|
PERF_PC_VPC_PRIMITIVES = 17,
|
|
PERF_PC_DEAD_PRIM = 18,
|
|
PERF_PC_LIVE_PRIM = 19,
|
|
PERF_PC_VERTEX_HITS = 20,
|
|
PERF_PC_IA_VERTICES = 21,
|
|
PERF_PC_IA_PRIMITIVES = 22,
|
|
PERF_PC_GS_PRIMITIVES = 23,
|
|
PERF_PC_HS_INVOCATIONS = 24,
|
|
PERF_PC_DS_INVOCATIONS = 25,
|
|
PERF_PC_VS_INVOCATIONS = 26,
|
|
PERF_PC_GS_INVOCATIONS = 27,
|
|
PERF_PC_DS_PRIMITIVES = 28,
|
|
PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
|
|
PERF_PC_3D_DRAWCALLS = 30,
|
|
PERF_PC_2D_DRAWCALLS = 31,
|
|
PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
|
|
PERF_TESS_BUSY_CYCLES = 33,
|
|
PERF_TESS_WORKING_CYCLES = 34,
|
|
PERF_TESS_STALL_CYCLES_PC = 35,
|
|
PERF_TESS_STARVE_CYCLES_PC = 36,
|
|
PERF_PC_TSE_TRANSACTION = 37,
|
|
PERF_PC_TSE_VERTEX = 38,
|
|
PERF_PC_TESS_PC_UV_TRANS = 39,
|
|
PERF_PC_TESS_PC_UV_PATCHES = 40,
|
|
PERF_PC_TESS_FACTOR_TRANS = 41,
|
|
};
|
|
|
|
enum a6xx_vfd_perfcounter_select {
|
|
PERF_VFD_BUSY_CYCLES = 0,
|
|
PERF_VFD_STALL_CYCLES_UCHE = 1,
|
|
PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
|
|
PERF_VFD_STALL_CYCLES_SP_INFO = 3,
|
|
PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
|
|
PERF_VFD_STARVE_CYCLES_UCHE = 5,
|
|
PERF_VFD_RBUFFER_FULL = 6,
|
|
PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
|
|
PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
|
|
PERF_VFD_NUM_ATTRIBUTES = 9,
|
|
PERF_VFD_UPPER_SHADER_FIBERS = 10,
|
|
PERF_VFD_LOWER_SHADER_FIBERS = 11,
|
|
PERF_VFD_MODE_0_FIBERS = 12,
|
|
PERF_VFD_MODE_1_FIBERS = 13,
|
|
PERF_VFD_MODE_2_FIBERS = 14,
|
|
PERF_VFD_MODE_3_FIBERS = 15,
|
|
PERF_VFD_MODE_4_FIBERS = 16,
|
|
PERF_VFD_TOTAL_VERTICES = 17,
|
|
PERF_VFDP_STALL_CYCLES_VFD = 18,
|
|
PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
|
|
PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
|
|
PERF_VFDP_STARVE_CYCLES_PC = 21,
|
|
PERF_VFDP_VS_STAGE_WAVES = 22,
|
|
};
|
|
|
|
enum a6xx_hlsq_perfcounter_select {
|
|
PERF_HLSQ_BUSY_CYCLES = 0,
|
|
PERF_HLSQ_STALL_CYCLES_UCHE = 1,
|
|
PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
|
|
PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
|
|
PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
|
|
PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
|
|
PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
|
|
PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
|
|
PERF_HLSQ_QUADS = 8,
|
|
PERF_HLSQ_CS_INVOCATIONS = 9,
|
|
PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
|
|
PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
|
|
PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
|
|
PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
|
|
PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
|
|
PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
|
|
PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
|
|
PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
|
|
PERF_HLSQ_STALL_CYCLES_VPC = 18,
|
|
PERF_HLSQ_PIXELS = 19,
|
|
PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
|
|
};
|
|
|
|
enum a6xx_vpc_perfcounter_select {
|
|
PERF_VPC_BUSY_CYCLES = 0,
|
|
PERF_VPC_WORKING_CYCLES = 1,
|
|
PERF_VPC_STALL_CYCLES_UCHE = 2,
|
|
PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
|
|
PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
|
|
PERF_VPC_STALL_CYCLES_PC = 5,
|
|
PERF_VPC_STALL_CYCLES_SP_LM = 6,
|
|
PERF_VPC_STARVE_CYCLES_SP = 7,
|
|
PERF_VPC_STARVE_CYCLES_LRZ = 8,
|
|
PERF_VPC_PC_PRIMITIVES = 9,
|
|
PERF_VPC_SP_COMPONENTS = 10,
|
|
PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
|
|
PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
|
|
PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
|
|
PERF_VPC_LM_TRANSACTION = 14,
|
|
PERF_VPC_STREAMOUT_TRANSACTION = 15,
|
|
PERF_VPC_VS_BUSY_CYCLES = 16,
|
|
PERF_VPC_PS_BUSY_CYCLES = 17,
|
|
PERF_VPC_VS_WORKING_CYCLES = 18,
|
|
PERF_VPC_PS_WORKING_CYCLES = 19,
|
|
PERF_VPC_STARVE_CYCLES_RB = 20,
|
|
PERF_VPC_NUM_VPCRAM_READ_POS = 21,
|
|
PERF_VPC_WIT_FULL_CYCLES = 22,
|
|
PERF_VPC_VPCRAM_FULL_CYCLES = 23,
|
|
PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
|
|
PERF_VPC_NUM_VPCRAM_WRITE = 25,
|
|
PERF_VPC_NUM_VPCRAM_READ_SO = 26,
|
|
PERF_VPC_NUM_ATTR_REQ_LM = 27,
|
|
};
|
|
|
|
enum a6xx_tse_perfcounter_select {
|
|
PERF_TSE_BUSY_CYCLES = 0,
|
|
PERF_TSE_CLIPPING_CYCLES = 1,
|
|
PERF_TSE_STALL_CYCLES_RAS = 2,
|
|
PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
|
|
PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
|
|
PERF_TSE_STARVE_CYCLES_PC = 5,
|
|
PERF_TSE_INPUT_PRIM = 6,
|
|
PERF_TSE_INPUT_NULL_PRIM = 7,
|
|
PERF_TSE_TRIVAL_REJ_PRIM = 8,
|
|
PERF_TSE_CLIPPED_PRIM = 9,
|
|
PERF_TSE_ZERO_AREA_PRIM = 10,
|
|
PERF_TSE_FACENESS_CULLED_PRIM = 11,
|
|
PERF_TSE_ZERO_PIXEL_PRIM = 12,
|
|
PERF_TSE_OUTPUT_NULL_PRIM = 13,
|
|
PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
|
|
PERF_TSE_CINVOCATION = 15,
|
|
PERF_TSE_CPRIMITIVES = 16,
|
|
PERF_TSE_2D_INPUT_PRIM = 17,
|
|
PERF_TSE_2D_ALIVE_CYCLES = 18,
|
|
PERF_TSE_CLIP_PLANES = 19,
|
|
};
|
|
|
|
enum a6xx_ras_perfcounter_select {
|
|
PERF_RAS_BUSY_CYCLES = 0,
|
|
PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
|
|
PERF_RAS_STALL_CYCLES_LRZ = 2,
|
|
PERF_RAS_STARVE_CYCLES_TSE = 3,
|
|
PERF_RAS_SUPER_TILES = 4,
|
|
PERF_RAS_8X4_TILES = 5,
|
|
PERF_RAS_MASKGEN_ACTIVE = 6,
|
|
PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
|
|
PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
|
|
PERF_RAS_PRIM_KILLED_INVISILBE = 9,
|
|
PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
|
|
PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
|
|
PERF_RAS_BLOCKS = 12,
|
|
};
|
|
|
|
enum a6xx_uche_perfcounter_select {
|
|
PERF_UCHE_BUSY_CYCLES = 0,
|
|
PERF_UCHE_STALL_CYCLES_ARBITER = 1,
|
|
PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
|
|
PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
|
|
PERF_UCHE_VBIF_READ_BEATS_TP = 4,
|
|
PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
|
|
PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
|
|
PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
|
|
PERF_UCHE_VBIF_READ_BEATS_SP = 8,
|
|
PERF_UCHE_READ_REQUESTS_TP = 9,
|
|
PERF_UCHE_READ_REQUESTS_VFD = 10,
|
|
PERF_UCHE_READ_REQUESTS_HLSQ = 11,
|
|
PERF_UCHE_READ_REQUESTS_LRZ = 12,
|
|
PERF_UCHE_READ_REQUESTS_SP = 13,
|
|
PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
|
|
PERF_UCHE_WRITE_REQUESTS_SP = 15,
|
|
PERF_UCHE_WRITE_REQUESTS_VPC = 16,
|
|
PERF_UCHE_WRITE_REQUESTS_VSC = 17,
|
|
PERF_UCHE_EVICTS = 18,
|
|
PERF_UCHE_BANK_REQ0 = 19,
|
|
PERF_UCHE_BANK_REQ1 = 20,
|
|
PERF_UCHE_BANK_REQ2 = 21,
|
|
PERF_UCHE_BANK_REQ3 = 22,
|
|
PERF_UCHE_BANK_REQ4 = 23,
|
|
PERF_UCHE_BANK_REQ5 = 24,
|
|
PERF_UCHE_BANK_REQ6 = 25,
|
|
PERF_UCHE_BANK_REQ7 = 26,
|
|
PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
|
|
PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
|
|
PERF_UCHE_GMEM_READ_BEATS = 29,
|
|
PERF_UCHE_TPH_REF_FULL = 30,
|
|
PERF_UCHE_TPH_VICTIM_FULL = 31,
|
|
PERF_UCHE_TPH_EXT_FULL = 32,
|
|
PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
|
|
PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
|
|
PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
|
|
PERF_UCHE_VBIF_READ_BEATS_PC = 36,
|
|
PERF_UCHE_READ_REQUESTS_PC = 37,
|
|
PERF_UCHE_RAM_READ_REQ = 38,
|
|
PERF_UCHE_RAM_WRITE_REQ = 39,
|
|
};
|
|
|
|
enum a6xx_tp_perfcounter_select {
|
|
PERF_TP_BUSY_CYCLES = 0,
|
|
PERF_TP_STALL_CYCLES_UCHE = 1,
|
|
PERF_TP_LATENCY_CYCLES = 2,
|
|
PERF_TP_LATENCY_TRANS = 3,
|
|
PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
|
|
PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
|
|
PERF_TP_L1_CACHELINE_REQUESTS = 6,
|
|
PERF_TP_L1_CACHELINE_MISSES = 7,
|
|
PERF_TP_SP_TP_TRANS = 8,
|
|
PERF_TP_TP_SP_TRANS = 9,
|
|
PERF_TP_OUTPUT_PIXELS = 10,
|
|
PERF_TP_FILTER_WORKLOAD_16BIT = 11,
|
|
PERF_TP_FILTER_WORKLOAD_32BIT = 12,
|
|
PERF_TP_QUADS_RECEIVED = 13,
|
|
PERF_TP_QUADS_OFFSET = 14,
|
|
PERF_TP_QUADS_SHADOW = 15,
|
|
PERF_TP_QUADS_ARRAY = 16,
|
|
PERF_TP_QUADS_GRADIENT = 17,
|
|
PERF_TP_QUADS_1D = 18,
|
|
PERF_TP_QUADS_2D = 19,
|
|
PERF_TP_QUADS_BUFFER = 20,
|
|
PERF_TP_QUADS_3D = 21,
|
|
PERF_TP_QUADS_CUBE = 22,
|
|
PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
|
|
PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
|
|
PERF_TP_OUTPUT_PIXELS_POINT = 25,
|
|
PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
|
|
PERF_TP_OUTPUT_PIXELS_MIP = 27,
|
|
PERF_TP_OUTPUT_PIXELS_ANISO = 28,
|
|
PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
|
|
PERF_TP_FLAG_CACHE_REQUESTS = 30,
|
|
PERF_TP_FLAG_CACHE_MISSES = 31,
|
|
PERF_TP_L1_5_L2_REQUESTS = 32,
|
|
PERF_TP_2D_OUTPUT_PIXELS = 33,
|
|
PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
|
|
PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
|
|
PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
|
|
PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
|
|
PERF_TP_TPA2TPC_TRANS = 38,
|
|
PERF_TP_L1_MISSES_ASTC_1TILE = 39,
|
|
PERF_TP_L1_MISSES_ASTC_2TILE = 40,
|
|
PERF_TP_L1_MISSES_ASTC_4TILE = 41,
|
|
PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
|
|
PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
|
|
PERF_TP_L1_BANK_CONFLICT = 44,
|
|
PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
|
|
PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
|
|
PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
|
|
PERF_TP_FRONTEND_WORKING_CYCLES = 48,
|
|
PERF_TP_L1_TAG_WORKING_CYCLES = 49,
|
|
PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
|
|
PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
|
|
PERF_TP_BACKEND_WORKING_CYCLES = 52,
|
|
PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
|
|
PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
|
|
PERF_TP_STARVE_CYCLES_SP = 55,
|
|
PERF_TP_STARVE_CYCLES_UCHE = 56,
|
|
};
|
|
|
|
enum a6xx_sp_perfcounter_select {
|
|
PERF_SP_BUSY_CYCLES = 0,
|
|
PERF_SP_ALU_WORKING_CYCLES = 1,
|
|
PERF_SP_EFU_WORKING_CYCLES = 2,
|
|
PERF_SP_STALL_CYCLES_VPC = 3,
|
|
PERF_SP_STALL_CYCLES_TP = 4,
|
|
PERF_SP_STALL_CYCLES_UCHE = 5,
|
|
PERF_SP_STALL_CYCLES_RB = 6,
|
|
PERF_SP_NON_EXECUTION_CYCLES = 7,
|
|
PERF_SP_WAVE_CONTEXTS = 8,
|
|
PERF_SP_WAVE_CONTEXT_CYCLES = 9,
|
|
PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
|
|
PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
|
|
PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
|
|
PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
|
|
PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
|
|
PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
|
|
PERF_SP_WAVE_CTRL_CYCLES = 16,
|
|
PERF_SP_WAVE_LOAD_CYCLES = 17,
|
|
PERF_SP_WAVE_EMIT_CYCLES = 18,
|
|
PERF_SP_WAVE_NOP_CYCLES = 19,
|
|
PERF_SP_WAVE_WAIT_CYCLES = 20,
|
|
PERF_SP_WAVE_FETCH_CYCLES = 21,
|
|
PERF_SP_WAVE_IDLE_CYCLES = 22,
|
|
PERF_SP_WAVE_END_CYCLES = 23,
|
|
PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
|
|
PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
|
|
PERF_SP_WAVE_JOIN_CYCLES = 26,
|
|
PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
|
|
PERF_SP_LM_STORE_INSTRUCTIONS = 28,
|
|
PERF_SP_LM_ATOMICS = 29,
|
|
PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
|
|
PERF_SP_GM_STORE_INSTRUCTIONS = 31,
|
|
PERF_SP_GM_ATOMICS = 32,
|
|
PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
|
|
PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
|
|
PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
|
|
PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
|
|
PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
|
|
PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
|
|
PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
|
|
PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
|
|
PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
|
|
PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
|
|
PERF_SP_VS_INSTRUCTIONS = 43,
|
|
PERF_SP_FS_INSTRUCTIONS = 44,
|
|
PERF_SP_ADDR_LOCK_COUNT = 45,
|
|
PERF_SP_UCHE_READ_TRANS = 46,
|
|
PERF_SP_UCHE_WRITE_TRANS = 47,
|
|
PERF_SP_EXPORT_VPC_TRANS = 48,
|
|
PERF_SP_EXPORT_RB_TRANS = 49,
|
|
PERF_SP_PIXELS_KILLED = 50,
|
|
PERF_SP_ICL1_REQUESTS = 51,
|
|
PERF_SP_ICL1_MISSES = 52,
|
|
PERF_SP_HS_INSTRUCTIONS = 53,
|
|
PERF_SP_DS_INSTRUCTIONS = 54,
|
|
PERF_SP_GS_INSTRUCTIONS = 55,
|
|
PERF_SP_CS_INSTRUCTIONS = 56,
|
|
PERF_SP_GPR_READ = 57,
|
|
PERF_SP_GPR_WRITE = 58,
|
|
PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
|
|
PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
|
|
PERF_SP_LM_BANK_CONFLICTS = 61,
|
|
PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
|
|
PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
|
|
PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
|
|
PERF_SP_LM_WORKING_CYCLES = 65,
|
|
PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
|
|
PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
|
|
PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
|
|
PERF_SP_STARVE_CYCLES_HLSQ = 69,
|
|
PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
|
|
PERF_SP_WORKING_EU = 71,
|
|
PERF_SP_ANY_EU_WORKING = 72,
|
|
PERF_SP_WORKING_EU_FS_STAGE = 73,
|
|
PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
|
|
PERF_SP_WORKING_EU_VS_STAGE = 75,
|
|
PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
|
|
PERF_SP_WORKING_EU_CS_STAGE = 77,
|
|
PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
|
|
PERF_SP_GPR_READ_PREFETCH = 79,
|
|
PERF_SP_GPR_READ_CONFLICT = 80,
|
|
PERF_SP_GPR_WRITE_CONFLICT = 81,
|
|
PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
|
|
PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
|
|
PERF_SP_EXECUTABLE_WAVES = 84,
|
|
};
|
|
|
|
enum a6xx_rb_perfcounter_select {
|
|
PERF_RB_BUSY_CYCLES = 0,
|
|
PERF_RB_STALL_CYCLES_HLSQ = 1,
|
|
PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
|
|
PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
|
|
PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
|
|
PERF_RB_STARVE_CYCLES_SP = 5,
|
|
PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
|
|
PERF_RB_STARVE_CYCLES_CCU = 7,
|
|
PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
|
|
PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
|
|
PERF_RB_Z_WORKLOAD = 10,
|
|
PERF_RB_HLSQ_ACTIVE = 11,
|
|
PERF_RB_Z_READ = 12,
|
|
PERF_RB_Z_WRITE = 13,
|
|
PERF_RB_C_READ = 14,
|
|
PERF_RB_C_WRITE = 15,
|
|
PERF_RB_TOTAL_PASS = 16,
|
|
PERF_RB_Z_PASS = 17,
|
|
PERF_RB_Z_FAIL = 18,
|
|
PERF_RB_S_FAIL = 19,
|
|
PERF_RB_BLENDED_FXP_COMPONENTS = 20,
|
|
PERF_RB_BLENDED_FP16_COMPONENTS = 21,
|
|
PERF_RB_PS_INVOCATIONS = 22,
|
|
PERF_RB_2D_ALIVE_CYCLES = 23,
|
|
PERF_RB_2D_STALL_CYCLES_A2D = 24,
|
|
PERF_RB_2D_STARVE_CYCLES_SRC = 25,
|
|
PERF_RB_2D_STARVE_CYCLES_SP = 26,
|
|
PERF_RB_2D_STARVE_CYCLES_DST = 27,
|
|
PERF_RB_2D_VALID_PIXELS = 28,
|
|
PERF_RB_3D_PIXELS = 29,
|
|
PERF_RB_BLENDER_WORKING_CYCLES = 30,
|
|
PERF_RB_ZPROC_WORKING_CYCLES = 31,
|
|
PERF_RB_CPROC_WORKING_CYCLES = 32,
|
|
PERF_RB_SAMPLER_WORKING_CYCLES = 33,
|
|
PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
|
|
PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
|
|
PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
|
|
PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
|
|
PERF_RB_STALL_CYCLES_VPC = 38,
|
|
PERF_RB_2D_INPUT_TRANS = 39,
|
|
PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
|
|
PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
|
|
PERF_RB_BLENDED_FP32_COMPONENTS = 42,
|
|
PERF_RB_COLOR_PIX_TILES = 43,
|
|
PERF_RB_STALL_CYCLES_CCU = 44,
|
|
PERF_RB_EARLY_Z_ARB3_GRANT = 45,
|
|
PERF_RB_LATE_Z_ARB3_GRANT = 46,
|
|
PERF_RB_EARLY_Z_SKIP_GRANT = 47,
|
|
};
|
|
|
|
enum a6xx_vsc_perfcounter_select {
|
|
PERF_VSC_BUSY_CYCLES = 0,
|
|
PERF_VSC_WORKING_CYCLES = 1,
|
|
PERF_VSC_STALL_CYCLES_UCHE = 2,
|
|
PERF_VSC_EOT_NUM = 3,
|
|
PERF_VSC_INPUT_TILES = 4,
|
|
};
|
|
|
|
enum a6xx_ccu_perfcounter_select {
|
|
PERF_CCU_BUSY_CYCLES = 0,
|
|
PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
|
|
PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
|
|
PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
|
|
PERF_CCU_DEPTH_BLOCKS = 4,
|
|
PERF_CCU_COLOR_BLOCKS = 5,
|
|
PERF_CCU_DEPTH_BLOCK_HIT = 6,
|
|
PERF_CCU_COLOR_BLOCK_HIT = 7,
|
|
PERF_CCU_PARTIAL_BLOCK_READ = 8,
|
|
PERF_CCU_GMEM_READ = 9,
|
|
PERF_CCU_GMEM_WRITE = 10,
|
|
PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
|
|
PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
|
|
PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
|
|
PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
|
|
PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
|
|
PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
|
|
PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
|
|
PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
|
|
PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
|
|
PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
|
|
PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
|
|
PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
|
|
PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
|
|
PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
|
|
PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
|
|
PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
|
|
PERF_CCU_2D_RD_REQ = 27,
|
|
PERF_CCU_2D_WR_REQ = 28,
|
|
};
|
|
|
|
enum a6xx_lrz_perfcounter_select {
|
|
PERF_LRZ_BUSY_CYCLES = 0,
|
|
PERF_LRZ_STARVE_CYCLES_RAS = 1,
|
|
PERF_LRZ_STALL_CYCLES_RB = 2,
|
|
PERF_LRZ_STALL_CYCLES_VSC = 3,
|
|
PERF_LRZ_STALL_CYCLES_VPC = 4,
|
|
PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
|
|
PERF_LRZ_STALL_CYCLES_UCHE = 6,
|
|
PERF_LRZ_LRZ_READ = 7,
|
|
PERF_LRZ_LRZ_WRITE = 8,
|
|
PERF_LRZ_READ_LATENCY = 9,
|
|
PERF_LRZ_MERGE_CACHE_UPDATING = 10,
|
|
PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
|
|
PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
|
|
PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
|
|
PERF_LRZ_FULL_8X8_TILES = 14,
|
|
PERF_LRZ_PARTIAL_8X8_TILES = 15,
|
|
PERF_LRZ_TILE_KILLED = 16,
|
|
PERF_LRZ_TOTAL_PIXEL = 17,
|
|
PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
|
|
PERF_LRZ_FULLY_COVERED_TILES = 19,
|
|
PERF_LRZ_PARTIAL_COVERED_TILES = 20,
|
|
PERF_LRZ_FEEDBACK_ACCEPT = 21,
|
|
PERF_LRZ_FEEDBACK_DISCARD = 22,
|
|
PERF_LRZ_FEEDBACK_STALL = 23,
|
|
PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
|
|
PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
|
|
PERF_LRZ_STALL_CYCLES_VC = 26,
|
|
PERF_LRZ_RAS_MASK_TRANS = 27,
|
|
};
|
|
|
|
enum a6xx_cmp_perfcounter_select {
|
|
PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
|
|
PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
|
|
PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
|
|
PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
|
|
PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
|
|
PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
|
|
PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
|
|
PERF_CMPDECMP_VBIF_READ_DATA = 7,
|
|
PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
|
|
PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
|
|
PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
|
|
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
|
|
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
|
|
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
|
|
PERF_CMPDECMP_2D_RD_DATA = 28,
|
|
PERF_CMPDECMP_2D_WR_DATA = 29,
|
|
PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
|
|
PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
|
|
PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
|
|
PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
|
|
PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
|
|
PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
|
|
PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
|
|
PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
|
|
PERF_CMPDECMP_2D_PIXELS = 39,
|
|
};
|
|
|
|
enum a6xx_tex_filter {
|
|
A6XX_TEX_NEAREST = 0,
|
|
A6XX_TEX_LINEAR = 1,
|
|
A6XX_TEX_ANISO = 2,
|
|
};
|
|
|
|
enum a6xx_tex_clamp {
|
|
A6XX_TEX_REPEAT = 0,
|
|
A6XX_TEX_CLAMP_TO_EDGE = 1,
|
|
A6XX_TEX_MIRROR_REPEAT = 2,
|
|
A6XX_TEX_CLAMP_TO_BORDER = 3,
|
|
A6XX_TEX_MIRROR_CLAMP = 4,
|
|
};
|
|
|
|
enum a6xx_tex_aniso {
|
|
A6XX_TEX_ANISO_1 = 0,
|
|
A6XX_TEX_ANISO_2 = 1,
|
|
A6XX_TEX_ANISO_4 = 2,
|
|
A6XX_TEX_ANISO_8 = 3,
|
|
A6XX_TEX_ANISO_16 = 4,
|
|
};
|
|
|
|
enum a6xx_tex_swiz {
|
|
A6XX_TEX_X = 0,
|
|
A6XX_TEX_Y = 1,
|
|
A6XX_TEX_Z = 2,
|
|
A6XX_TEX_W = 3,
|
|
A6XX_TEX_ZERO = 4,
|
|
A6XX_TEX_ONE = 5,
|
|
};
|
|
|
|
enum a6xx_tex_type {
|
|
A6XX_TEX_1D = 0,
|
|
A6XX_TEX_2D = 1,
|
|
A6XX_TEX_CUBE = 2,
|
|
A6XX_TEX_3D = 3,
|
|
};
|
|
|
|
#define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
|
|
#define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002
|
|
#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040
|
|
#define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
|
|
#define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100
|
|
#define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
|
|
#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
|
|
#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
|
|
#define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
|
|
#define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
|
|
#define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
|
|
#define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000
|
|
#define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
|
|
#define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
|
|
#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
|
|
#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
|
|
#define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000
|
|
#define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
|
|
#define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
|
|
#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
|
|
#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
|
|
#define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
|
|
#define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
|
|
#define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
|
|
#define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
|
|
#define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
|
|
#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
|
|
#define A6XX_CP_INT_CP_AHB_ERROR 0x00000020
|
|
#define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040
|
|
#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080
|
|
#define REG_A6XX_CP_RB_BASE 0x00000800
|
|
|
|
#define REG_A6XX_CP_RB_BASE_HI 0x00000801
|
|
|
|
#define REG_A6XX_CP_RB_CNTL 0x00000802
|
|
|
|
#define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804
|
|
|
|
#define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805
|
|
|
|
#define REG_A6XX_CP_RB_RPTR 0x00000806
|
|
|
|
#define REG_A6XX_CP_RB_WPTR 0x00000807
|
|
|
|
#define REG_A6XX_CP_SQE_CNTL 0x00000808
|
|
|
|
#define REG_A6XX_CP_HW_FAULT 0x00000821
|
|
|
|
#define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
|
|
|
|
#define REG_A6XX_CP_PROTECT_STATUS 0x00000824
|
|
|
|
#define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830
|
|
|
|
#define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831
|
|
|
|
#define REG_A6XX_CP_MISC_CNTL 0x00000840
|
|
|
|
#define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
|
|
|
|
#define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
|
|
|
|
#define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
|
|
|
|
#define REG_A6XX_CP_CHICKEN_DBG 0x00000841
|
|
|
|
#define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842
|
|
|
|
#define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
|
|
|
|
#define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
|
|
|
|
static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
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static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
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static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
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#define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
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#define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
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static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
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{
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return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
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}
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#define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000
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#define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18
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static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
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{
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return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
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}
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#define A6XX_CP_PROTECT_REG_READ 0x80000000
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#define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0
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#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1
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#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2
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#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3
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#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4
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#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5
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#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6
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#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
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#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
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#define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0
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#define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1
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#define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2
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#define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3
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#define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4
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#define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5
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#define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6
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#define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7
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#define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8
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#define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9
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#define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da
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#define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db
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#define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc
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#define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd
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#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
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#define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901
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#define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
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#define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
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#define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908
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#define REG_A6XX_CP_SQE_STAT_DATA 0x00000909
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#define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a
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#define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b
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#define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c
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#define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d
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#define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e
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#define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f
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#define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910
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#define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911
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#define REG_A6XX_CP_IB1_BASE 0x00000928
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#define REG_A6XX_CP_IB1_BASE_HI 0x00000929
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#define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a
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#define REG_A6XX_CP_IB2_BASE 0x0000092b
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#define REG_A6XX_CP_IB2_BASE_HI 0x0000092c
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#define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
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#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
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#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
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#define REG_A6XX_CP_AHB_CNTL 0x0000098d
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#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
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#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
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#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
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#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
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#define REG_A6XX_RBBM_STATUS 0x00000210
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#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
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#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
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#define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000
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#define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000
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#define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000
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#define A6XX_RBBM_STATUS_SP_BUSY 0x00040000
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#define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000
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#define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000
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#define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000
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#define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000
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#define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000
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#define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000
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#define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800
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#define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400
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#define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200
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#define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100
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#define A6XX_RBBM_STATUS_RB_BUSY 0x00000080
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#define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040
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#define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020
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#define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010
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#define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008
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#define A6XX_RBBM_STATUS_CP_BUSY 0x00000004
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#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
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#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
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#define REG_A6XX_RBBM_STATUS3 0x00000213
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#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
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#define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400
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#define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401
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#define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402
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#define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403
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#define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404
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#define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405
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#define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406
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#define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407
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#define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408
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#define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409
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#define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a
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#define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b
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#define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c
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#define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d
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#define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e
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#define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f
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#define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410
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#define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411
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#define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412
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#define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413
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#define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414
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#define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415
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#define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416
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#define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417
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#define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418
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#define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419
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#define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a
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#define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b
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#define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c
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#define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d
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#define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e
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#define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f
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#define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420
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#define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421
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#define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422
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#define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423
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#define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424
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#define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425
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#define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426
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#define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427
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#define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428
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#define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429
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#define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a
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#define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b
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#define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c
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#define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d
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#define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e
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#define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f
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#define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430
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#define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431
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#define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432
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#define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433
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#define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434
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#define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435
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#define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436
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#define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437
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#define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438
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#define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439
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#define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a
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#define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b
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#define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c
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#define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d
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#define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e
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#define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f
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#define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440
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#define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441
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#define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442
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#define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e
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#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f
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#define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450
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#define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451
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#define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452
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#define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453
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#define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454
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#define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455
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#define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456
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#define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457
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#define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458
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#define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459
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#define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a
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#define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b
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#define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c
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#define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d
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#define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e
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#define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f
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#define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460
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#define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461
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#define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462
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#define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463
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#define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464
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#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
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#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
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#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
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#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
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#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
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#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
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#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
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#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
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#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
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#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
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#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
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#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
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#define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
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#define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
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#define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d
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#define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e
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#define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f
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#define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470
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#define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471
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#define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472
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#define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473
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#define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474
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#define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475
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#define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476
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#define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477
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#define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478
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#define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479
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#define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a
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#define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b
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#define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c
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#define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d
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#define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e
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#define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f
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#define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480
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#define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481
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#define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482
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#define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483
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#define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484
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#define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485
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#define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486
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#define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487
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#define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488
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#define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489
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#define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a
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#define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b
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#define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c
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#define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d
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#define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e
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#define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f
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#define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490
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#define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491
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#define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492
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#define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493
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#define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494
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#define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495
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#define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496
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#define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497
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#define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498
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#define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499
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#define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a
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#define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b
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#define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c
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#define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d
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#define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e
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#define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f
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#define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0
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#define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1
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#define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2
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#define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3
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#define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4
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#define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5
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#define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6
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#define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7
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#define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8
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#define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9
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#define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa
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#define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab
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#define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac
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#define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad
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#define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae
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#define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af
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#define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0
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#define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1
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#define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2
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#define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3
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#define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4
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#define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5
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#define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6
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#define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7
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#define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8
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#define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9
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#define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba
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#define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb
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#define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc
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#define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd
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#define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be
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#define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf
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#define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0
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#define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1
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#define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2
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#define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3
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#define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4
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#define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5
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#define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6
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#define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7
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#define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8
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#define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9
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#define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca
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#define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb
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#define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc
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#define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd
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#define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce
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#define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf
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#define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0
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#define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1
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#define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2
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#define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3
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#define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4
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#define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5
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#define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6
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#define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7
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#define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8
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#define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9
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#define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da
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#define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db
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#define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc
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#define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd
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#define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de
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#define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df
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#define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0
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#define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1
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#define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2
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#define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3
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#define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4
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#define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5
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#define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6
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#define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7
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#define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8
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#define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9
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#define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea
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#define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb
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#define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec
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#define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed
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#define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee
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#define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef
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#define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0
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#define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1
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#define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2
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#define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3
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#define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4
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#define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5
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#define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6
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#define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7
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#define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8
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#define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9
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#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
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#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
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#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
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#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
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#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
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#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
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#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
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#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507
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#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508
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#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509
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#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a
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#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
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#define REG_A6XX_RBBM_ISDB_CNT 0x00000533
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#define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
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#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
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#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
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#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
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#define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803
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#define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
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#define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
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#define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
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#define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
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#define REG_A6XX_RBBM_INT_0_MASK 0x00000038
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#define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
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#define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043
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#define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044
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#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
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#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
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#define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
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#define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
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#define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1
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#define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2
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#define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3
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#define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4
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#define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5
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#define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6
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#define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7
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#define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8
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#define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9
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#define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba
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#define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb
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#define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc
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#define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd
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#define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be
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#define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf
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#define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0
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#define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1
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#define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2
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#define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3
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#define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4
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#define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5
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#define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6
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#define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7
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#define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8
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#define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9
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#define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca
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#define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb
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#define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc
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#define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd
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#define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce
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#define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf
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#define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0
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#define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1
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#define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2
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#define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3
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#define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4
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#define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5
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#define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6
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#define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7
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#define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8
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#define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9
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#define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da
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#define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db
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#define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc
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#define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd
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#define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de
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#define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df
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#define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0
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#define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1
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#define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2
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#define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3
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#define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4
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#define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5
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#define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6
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#define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7
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#define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8
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#define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9
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#define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea
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#define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb
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#define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec
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#define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed
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#define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee
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#define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef
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#define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0
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#define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1
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#define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2
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#define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3
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#define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4
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#define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5
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#define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6
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#define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7
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#define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8
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#define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9
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#define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa
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#define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb
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#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100
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#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101
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#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102
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#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103
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#define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104
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#define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105
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#define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106
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#define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107
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#define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108
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#define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109
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#define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a
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#define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b
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#define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c
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#define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d
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#define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e
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#define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f
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#define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110
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#define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111
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#define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112
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#define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113
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#define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114
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#define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115
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#define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116
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#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117
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#define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118
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#define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119
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#define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a
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#define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b
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#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
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#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
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#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
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#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602
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#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603
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#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
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#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
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static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
|
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{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
|
|
}
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#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
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#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
|
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static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
|
|
{
|
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return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
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}
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#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604
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#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
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#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
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static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
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|
}
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#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
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#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
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static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
|
|
}
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|
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
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#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
|
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static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
|
|
}
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|
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#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605
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#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
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#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
|
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static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
|
|
}
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|
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#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608
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#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609
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#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a
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#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b
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#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c
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#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d
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#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e
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#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f
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#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610
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#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
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#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
|
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#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
|
|
}
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
|
|
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
|
|
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
|
|
|
|
#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
|
|
|
|
#define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8
|
|
|
|
#define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9
|
|
|
|
#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a
|
|
|
|
#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b
|
|
|
|
#define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
|
|
|
|
#define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08
|
|
|
|
#define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10
|
|
|
|
#define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11
|
|
|
|
#define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12
|
|
|
|
#define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13
|
|
|
|
#define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14
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#define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15
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#define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16
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#define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17
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#define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18
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#define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19
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#define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a
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#define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b
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#define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c
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#define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c
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#define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d
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#define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e
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#define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f
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#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
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#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
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#define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
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#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
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#define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34
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#define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35
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#define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36
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#define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37
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#define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38
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#define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39
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#define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a
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#define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b
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#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
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#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10
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#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11
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#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12
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#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13
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#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14
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#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15
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#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
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#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
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#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
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#define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610
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#define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611
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#define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612
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#define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613
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#define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614
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#define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615
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#define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616
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#define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617
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#define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
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#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604
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#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605
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#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606
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#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607
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#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608
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#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609
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#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
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#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
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#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
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#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
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#define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
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#define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
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#define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
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#define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
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#define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
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#define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
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#define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
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#define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
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#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
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#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
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#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
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#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
|
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#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
|
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static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
|
|
}
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26
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#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27
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#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
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#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
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#define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10
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#define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11
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#define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12
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#define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13
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#define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14
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#define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15
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#define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16
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#define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17
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#define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18
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#define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19
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#define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a
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#define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b
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#define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c
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#define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d
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#define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e
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#define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f
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#define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20
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#define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21
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#define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22
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#define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23
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#define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24
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#define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25
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#define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26
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#define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27
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#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
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#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a
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#define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b
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#define REG_A6XX_VBIF_VERSION 0x00003000
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#define REG_A6XX_VBIF_CLKON 0x00003001
|
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#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
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#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
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#define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
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#define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
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|
#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
|
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|
#define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085
|
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|
|
#define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086
|
|
#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f
|
|
#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0
|
|
static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087
|
|
|
|
#define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088
|
|
#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff
|
|
#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0
|
|
static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c
|
|
|
|
#define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
|
|
|
|
#define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
|
|
|
|
#define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2
|
|
|
|
#define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3
|
|
|
|
#define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8
|
|
|
|
#define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9
|
|
|
|
#define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da
|
|
|
|
#define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db
|
|
|
|
#define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0
|
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|
|
#define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1
|
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|
|
#define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2
|
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|
|
#define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3
|
|
|
|
#define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
|
|
|
|
#define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
|
|
|
|
#define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
|
|
|
|
#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
|
|
|
|
#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
|
|
|
|
#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
|
|
|
|
#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
|
|
|
|
#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
|
|
|
|
#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
|
|
|
|
#define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
|
|
#define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00007fff
|
|
#define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0
|
|
static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
|
|
}
|
|
#define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x7fff0000
|
|
#define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16
|
|
static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
|
|
#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff
|
|
#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
|
|
static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
|
|
}
|
|
#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000
|
|
#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
|
|
static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
|
|
#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff
|
|
#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
|
|
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
|
|
}
|
|
#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000
|
|
#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
|
|
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
|
|
#define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x000000ff
|
|
#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
|
|
}
|
|
#define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x0001ff00
|
|
#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
|
|
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
|
|
{
|
|
return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
|
|
}
|
|
#define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000
|
|
#define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000
|
|
|
|
#define REG_A6XX_RB_BIN_CONTROL2 0x000088d3
|
|
#define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x000000ff
|
|
#define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
|
|
}
|
|
#define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x0001ff00
|
|
#define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8
|
|
static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
|
|
{
|
|
return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
|
|
#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
|
|
#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
|
|
static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
|
|
}
|
|
#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
|
|
#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
|
|
static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VSC_SIZE_ADDRESS_LO 0x00000c03
|
|
|
|
#define REG_A6XX_VSC_SIZE_ADDRESS_HI 0x00000c04
|
|
|
|
#define REG_A6XX_VSC_BIN_COUNT 0x00000c06
|
|
#define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
|
|
#define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
|
|
static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
|
|
}
|
|
#define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800
|
|
#define A6XX_VSC_BIN_COUNT_NY__SHIFT 11
|
|
static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
|
|
#define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
|
|
#define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
|
|
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
|
|
}
|
|
#define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
|
|
#define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
|
|
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
|
|
}
|
|
#define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000
|
|
#define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
|
|
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
|
|
}
|
|
#define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
|
|
#define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
|
|
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO 0x00000c30
|
|
|
|
#define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI 0x00000c31
|
|
|
|
#define REG_A6XX_VSC_PIPE_DATA2_PITCH 0x00000c32
|
|
|
|
#define REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH 0x00000c33
|
|
#define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO 0x00000c34
|
|
|
|
#define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI 0x00000c35
|
|
|
|
#define REG_A6XX_VSC_PIPE_DATA_PITCH 0x00000c36
|
|
|
|
#define REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH 0x00000c37
|
|
#define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
|
|
|
|
#define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_8000 0x00008000
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004
|
|
|
|
#define REG_A6XX_GRAS_CNTL 0x00008005
|
|
#define A6XX_GRAS_CNTL_VARYING 0x00000001
|
|
#define A6XX_GRAS_CNTL_UNK3 0x00000008
|
|
#define A6XX_GRAS_CNTL_XCOORD 0x00000040
|
|
#define A6XX_GRAS_CNTL_YCOORD 0x00000080
|
|
#define A6XX_GRAS_CNTL_ZCOORD 0x00000100
|
|
#define A6XX_GRAS_CNTL_WCOORD 0x00000200
|
|
|
|
#define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
|
|
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
|
|
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
|
|
}
|
|
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
|
|
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
|
|
static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0 0x00008010
|
|
#define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
|
|
#define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_CL_VPORT_XSCALE_0 0x00008011
|
|
#define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
|
|
#define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0 0x00008012
|
|
#define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
|
|
#define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_CL_VPORT_YSCALE_0 0x00008013
|
|
#define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
|
|
#define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0 0x00008014
|
|
#define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
|
|
#define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0 0x00008015
|
|
#define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
|
|
#define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_SU_CNTL 0x00008090
|
|
#define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
|
|
#define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
|
|
#define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
|
|
#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
|
|
#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
|
|
static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
|
|
{
|
|
return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
|
|
}
|
|
#define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
|
|
#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
|
|
|
|
#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
|
|
#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
|
|
#define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
|
|
{
|
|
return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
|
|
}
|
|
#define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
|
|
#define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
|
|
static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
|
|
{
|
|
return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092
|
|
#define A6XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
|
|
#define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
|
|
{
|
|
return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
|
|
#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
|
|
|
|
#define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
|
|
#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
|
|
#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096
|
|
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
|
|
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097
|
|
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
|
|
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098
|
|
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
|
|
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
|
|
{
|
|
return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0
|
|
|
|
#define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
|
|
#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
|
|
#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
#define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_80A4 0x000080a4
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_80A5 0x000080a5
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_80A6 0x000080a6
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
|
|
|
|
#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x000080b0
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
|
|
}
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
|
|
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x000080b1
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
|
|
}
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
|
|
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
|
|
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x000080d0
|
|
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
|
|
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
|
|
{
|
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return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
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}
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#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
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#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
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static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
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{
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return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
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}
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#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x000080d1
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#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
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#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
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#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
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static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
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{
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return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
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}
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#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
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#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
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static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
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{
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return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
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}
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#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
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static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
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{
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return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
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}
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
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static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
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{
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return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
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}
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#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
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static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
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{
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return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
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}
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
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#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
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static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
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{
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return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
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}
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#define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
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#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
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#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
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#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
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#define A6XX_GRAS_LRZ_CNTL_UNK3 0x00000008
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#define A6XX_GRAS_LRZ_CNTL_UNK4 0x00000010
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#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
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#define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
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#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
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#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
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static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
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|
{
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return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
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}
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#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103
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#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104
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#define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
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#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000007ff
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#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
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static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
|
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{
|
|
return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
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|
}
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#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800
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#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
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static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
|
|
}
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#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106
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#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
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#define REG_A6XX_GRAS_UNKNOWN_8109 0x00008109
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#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
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#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
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#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
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#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
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static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
|
|
{
|
|
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
|
|
}
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#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
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#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
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#define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0x00ffff00
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#define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT 8
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static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK;
|
|
}
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#define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
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#define A6XX_GRAS_2D_SRC_BR_X_X__MASK 0x00ffff00
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#define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT 8
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static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK;
|
|
}
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|
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#define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
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|
#define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK 0x00ffff00
|
|
#define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT 8
|
|
static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK;
|
|
}
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#define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
|
|
#define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK 0x00ffff00
|
|
#define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT 8
|
|
static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK;
|
|
}
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|
|
#define REG_A6XX_GRAS_2D_DST_TL 0x00008405
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|
#define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_GRAS_2D_DST_TL_X__MASK 0x00007fff
|
|
#define A6XX_GRAS_2D_DST_TL_X__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
|
|
}
|
|
#define A6XX_GRAS_2D_DST_TL_Y__MASK 0x7fff0000
|
|
#define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16
|
|
static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_2D_DST_BR 0x00008406
|
|
#define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_GRAS_2D_DST_BR_X__MASK 0x00007fff
|
|
#define A6XX_GRAS_2D_DST_BR_X__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
|
|
}
|
|
#define A6XX_GRAS_2D_DST_BR_Y__MASK 0x7fff0000
|
|
#define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16
|
|
static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_RESOLVE_CNTL_1 0x0000840a
|
|
#define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK 0x00007fff
|
|
#define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK;
|
|
}
|
|
#define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
|
|
#define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT 16
|
|
static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_RESOLVE_CNTL_2 0x0000840b
|
|
#define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK 0x00007fff
|
|
#define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT 0
|
|
static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK;
|
|
}
|
|
#define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
|
|
#define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT 16
|
|
static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
|
|
|
|
#define REG_A6XX_RB_BIN_CONTROL 0x00008800
|
|
#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x000000ff
|
|
#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
|
|
}
|
|
#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x0001ff00
|
|
#define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
|
|
static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
|
|
{
|
|
return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
|
|
}
|
|
#define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000
|
|
#define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000
|
|
|
|
#define REG_A6XX_RB_RENDER_CNTL 0x00008801
|
|
#define A6XX_RB_RENDER_CNTL_UNK4 0x00000010
|
|
#define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
|
|
#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
|
|
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
|
|
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
|
|
static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
|
|
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
|
|
#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
#define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8804 0x00008804
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8805 0x00008805
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8806 0x00008806
|
|
|
|
#define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
|
|
#define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001
|
|
#define A6XX_RB_RENDER_CONTROL0_UNK3 0x00000008
|
|
#define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
|
|
#define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
|
|
#define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
|
|
#define A6XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
|
|
#define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
|
|
|
|
#define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
|
|
#define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
|
|
#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
|
|
#define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
|
|
|
|
#define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
|
|
#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
|
|
|
|
#define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
|
|
#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
|
|
#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0
|
|
static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
|
|
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
|
|
}
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
|
|
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
|
|
}
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
|
|
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
|
|
}
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
|
|
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
|
|
}
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
|
|
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
|
|
}
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
|
|
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
|
|
}
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
|
|
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
|
|
}
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
|
|
#define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
|
|
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_DITHER_CNTL 0x0000880e
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0
|
|
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
|
|
}
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2
|
|
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
|
|
}
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4
|
|
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
|
|
}
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6
|
|
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
|
|
}
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8
|
|
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
|
|
}
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10
|
|
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
|
|
}
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
|
|
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
|
|
}
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000
|
|
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14
|
|
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_SRGB_CNTL 0x0000880f
|
|
#define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001
|
|
#define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002
|
|
#define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004
|
|
#define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008
|
|
#define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010
|
|
#define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020
|
|
#define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
|
|
#define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8810 0x00008810
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8811 0x00008811
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8818 0x00008818
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8819 0x00008819
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_881A 0x0000881a
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_881B 0x0000881b
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_881C 0x0000881c
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_881D 0x0000881d
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
|
|
#define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
|
|
#define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002
|
|
#define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
|
|
#define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
|
|
#define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
|
|
static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
|
|
}
|
|
#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
|
|
#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
|
|
static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
|
|
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
|
|
}
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
|
|
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
|
|
}
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
|
|
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
|
|
}
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
|
|
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
|
|
}
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
|
|
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
|
|
}
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
|
|
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
|
|
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
|
|
#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
|
|
#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
|
|
static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
|
|
}
|
|
#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
|
|
#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
|
|
static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
|
|
#define A6XX_RB_MRT_PITCH__MASK 0xffffffff
|
|
#define A6XX_RB_MRT_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
|
|
#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
|
|
|
|
#define REG_A6XX_RB_BLEND_RED_F32 0x00008860
|
|
#define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff
|
|
#define A6XX_RB_BLEND_RED_F32__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861
|
|
#define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
|
|
#define A6XX_RB_BLEND_GREEN_F32__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862
|
|
#define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
|
|
#define A6XX_RB_BLEND_BLUE_F32__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863
|
|
#define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
|
|
#define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
|
|
{
|
|
return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_ALPHA_CONTROL 0x00008864
|
|
#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
|
|
#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
|
|
static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
|
|
}
|
|
#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
|
|
#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
|
|
#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
|
|
static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_BLEND_CNTL 0x00008865
|
|
#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
|
|
#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
|
|
}
|
|
#define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
|
|
#define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
|
|
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
|
|
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
|
|
static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870
|
|
#define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
|
|
|
|
#define REG_A6XX_RB_DEPTH_CNTL 0x00008871
|
|
#define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
|
|
#define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
|
|
#define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
|
|
#define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
|
|
static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
|
|
}
|
|
#define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
|
|
|
|
#define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
|
|
#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
|
|
#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
|
|
static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
|
|
{
|
|
return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873
|
|
#define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
|
|
#define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
|
|
#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875
|
|
|
|
#define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876
|
|
|
|
#define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8878 0x00008878
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8879 0x00008879
|
|
|
|
#define REG_A6XX_RB_STENCIL_CONTROL 0x00008880
|
|
#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
|
|
#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
|
|
#define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
|
|
#define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
|
|
#define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
|
|
static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
|
|
}
|
|
#define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
|
|
#define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
|
|
static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
|
|
}
|
|
#define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
|
|
#define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
|
|
static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
|
|
}
|
|
#define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
|
|
#define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
|
|
static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
|
|
}
|
|
#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
|
|
#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
|
|
static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
|
|
}
|
|
#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
|
|
#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
|
|
static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
|
|
}
|
|
#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
|
|
#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
|
|
static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
|
|
}
|
|
#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
|
|
#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
|
|
static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_STENCIL_INFO 0x00008881
|
|
#define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
|
|
|
|
#define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882
|
|
#define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0xffffffff
|
|
#define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
|
|
#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884
|
|
|
|
#define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885
|
|
|
|
#define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
|
|
|
|
#define REG_A6XX_RB_STENCILREF 0x00008887
|
|
#define A6XX_RB_STENCILREF_REF__MASK 0x000000ff
|
|
#define A6XX_RB_STENCILREF_REF__SHIFT 0
|
|
static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
|
|
}
|
|
#define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00
|
|
#define A6XX_RB_STENCILREF_BFREF__SHIFT 8
|
|
static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_STENCILMASK 0x00008888
|
|
#define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff
|
|
#define A6XX_RB_STENCILMASK_MASK__SHIFT 0
|
|
static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
|
|
}
|
|
#define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00
|
|
#define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8
|
|
static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_STENCILWRMASK 0x00008889
|
|
#define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff
|
|
#define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0
|
|
static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
|
|
}
|
|
#define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00
|
|
#define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8
|
|
static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_WINDOW_OFFSET 0x00008890
|
|
#define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
|
|
#define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0
|
|
static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
|
|
}
|
|
#define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
|
|
#define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16
|
|
static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
|
|
#define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
|
|
|
|
#define REG_A6XX_RB_LRZ_CNTL 0x00008898
|
|
#define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
|
|
|
|
#define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
|
|
#define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00007fff
|
|
#define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
|
|
}
|
|
#define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x7fff0000
|
|
#define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16
|
|
static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2
|
|
#define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
|
|
#define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00007fff
|
|
#define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
|
|
}
|
|
#define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x7fff0000
|
|
#define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16
|
|
static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_MSAA_CNTL 0x000088d5
|
|
#define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018
|
|
#define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3
|
|
static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
|
|
|
|
#define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
|
|
#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003
|
|
#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
|
|
}
|
|
#define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
|
|
#define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018
|
|
#define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3
|
|
static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
|
|
}
|
|
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
|
|
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
|
|
static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
|
|
{
|
|
return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060
|
|
#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5
|
|
static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_BLIT_DST_LO 0x000088d8
|
|
|
|
#define REG_A6XX_RB_BLIT_DST_HI 0x000088d9
|
|
|
|
#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
|
|
#define A6XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
|
|
#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db
|
|
#define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
|
|
#define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc
|
|
|
|
#define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
|
|
|
|
#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
|
|
|
|
#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
|
|
|
|
#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
|
|
|
|
#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
|
|
|
|
#define REG_A6XX_RB_BLIT_INFO 0x000088e3
|
|
#define A6XX_RB_BLIT_INFO_UNK0 0x00000001
|
|
#define A6XX_RB_BLIT_INFO_GMEM 0x00000002
|
|
#define A6XX_RB_BLIT_INFO_INTEGER 0x00000004
|
|
#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
|
|
#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
|
|
#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
|
|
static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
|
|
|
|
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900
|
|
|
|
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
|
|
|
|
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
|
|
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
|
|
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
|
|
}
|
|
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800
|
|
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
|
|
static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927
|
|
|
|
#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928
|
|
|
|
#define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
|
|
#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
|
|
#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
|
|
static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
|
|
{
|
|
return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8C01 0x00008c01
|
|
|
|
#define REG_A6XX_RB_2D_DST_INFO 0x00008c17
|
|
#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
|
|
{
|
|
return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
|
|
#define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
|
|
static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
|
|
{
|
|
return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
|
|
}
|
|
#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
|
|
#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
|
|
static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
#define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000
|
|
|
|
#define REG_A6XX_RB_2D_DST_LO 0x00008c18
|
|
|
|
#define REG_A6XX_RB_2D_DST_HI 0x00008c19
|
|
|
|
#define REG_A6XX_RB_2D_DST_SIZE 0x00008c1a
|
|
#define A6XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
|
|
#define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20
|
|
|
|
#define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
|
|
|
|
#define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
|
|
|
|
#define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
|
|
|
|
#define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e
|
|
|
|
#define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01
|
|
|
|
#define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04
|
|
|
|
#define REG_A6XX_RB_CCU_CNTL 0x00008e07
|
|
|
|
#define REG_A6XX_VPC_UNKNOWN_9101 0x00009101
|
|
|
|
#define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104
|
|
|
|
#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
|
|
|
|
#define REG_A6XX_VPC_UNKNOWN_9108 0x00009108
|
|
|
|
static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
|
|
|
|
#define REG_A6XX_VPC_UNKNOWN_9210 0x00009210
|
|
|
|
#define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
|
|
|
|
static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
|
|
|
|
#define REG_A6XX_VPC_SO_CNTL 0x00009216
|
|
#define A6XX_VPC_SO_CNTL_ENABLE 0x00010000
|
|
|
|
#define REG_A6XX_VPC_SO_PROG 0x00009217
|
|
#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
|
|
#define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
|
|
static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
|
|
}
|
|
#define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
|
|
#define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2
|
|
static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
|
|
}
|
|
#define A6XX_VPC_SO_PROG_A_EN 0x00000800
|
|
#define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
|
|
#define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12
|
|
static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
|
|
}
|
|
#define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
|
|
#define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
|
|
static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
|
|
}
|
|
#define A6XX_VPC_SO_PROG_B_EN 0x00800000
|
|
|
|
static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
|
|
|
|
#define REG_A6XX_VPC_UNKNOWN_9236 0x00009236
|
|
|
|
#define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
|
|
|
|
#define REG_A6XX_VPC_PACK 0x00009301
|
|
#define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK 0x000000ff
|
|
#define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT 0
|
|
static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK;
|
|
}
|
|
#define A6XX_VPC_PACK_NUMNONPOSVAR__MASK 0x0000ff00
|
|
#define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT 8
|
|
static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK;
|
|
}
|
|
#define A6XX_VPC_PACK_PSIZELOC__MASK 0x00ff0000
|
|
#define A6XX_VPC_PACK_PSIZELOC__SHIFT 16
|
|
static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VPC_CNTL_0 0x00009304
|
|
#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
|
|
#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
|
|
static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
|
|
}
|
|
#define A6XX_VPC_CNTL_0_VARYING 0x00010000
|
|
|
|
#define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305
|
|
#define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
|
|
#define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
|
|
#define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
|
|
#define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
|
|
#define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
|
|
|
|
#define REG_A6XX_VPC_SO_OVERRIDE 0x00009306
|
|
#define A6XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
|
|
|
|
#define REG_A6XX_VPC_UNKNOWN_9600 0x00009600
|
|
|
|
#define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
|
|
|
|
#define REG_A6XX_PC_UNKNOWN_9801 0x00009801
|
|
|
|
#define REG_A6XX_PC_RESTART_INDEX 0x00009803
|
|
|
|
#define REG_A6XX_PC_MODE_CNTL 0x00009804
|
|
|
|
#define REG_A6XX_PC_UNKNOWN_9805 0x00009805
|
|
|
|
#define REG_A6XX_PC_UNKNOWN_9806 0x00009806
|
|
|
|
#define REG_A6XX_PC_UNKNOWN_9980 0x00009980
|
|
|
|
#define REG_A6XX_PC_UNKNOWN_9981 0x00009981
|
|
|
|
#define REG_A6XX_PC_UNKNOWN_9990 0x00009990
|
|
|
|
#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
|
|
#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
|
|
#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
|
|
|
|
#define REG_A6XX_PC_PRIMITIVE_CNTL_1 0x00009b01
|
|
#define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK 0x0000007f
|
|
#define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT 0
|
|
static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK;
|
|
}
|
|
#define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE 0x00000100
|
|
|
|
#define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06
|
|
|
|
#define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07
|
|
|
|
#define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08
|
|
|
|
#define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09
|
|
|
|
#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
|
|
|
|
#define REG_A6XX_VFD_CONTROL_0 0x0000a000
|
|
#define A6XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
|
|
#define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
|
|
static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VFD_CONTROL_1 0x0000a001
|
|
#define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
|
|
#define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
|
|
static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
|
|
}
|
|
#define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
|
|
#define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
|
|
static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
|
|
}
|
|
#define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
|
|
#define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
|
|
static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VFD_CONTROL_2 0x0000a002
|
|
#define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
|
|
#define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
|
|
static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VFD_CONTROL_3 0x0000a003
|
|
#define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
|
|
#define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
|
|
static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
|
|
}
|
|
#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
|
|
#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
|
|
static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
|
|
}
|
|
#define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
|
|
#define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
|
|
static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_VFD_CONTROL_4 0x0000a004
|
|
|
|
#define REG_A6XX_VFD_CONTROL_5 0x0000a005
|
|
|
|
#define REG_A6XX_VFD_CONTROL_6 0x0000a006
|
|
|
|
#define REG_A6XX_VFD_MODE_CNTL 0x0000a007
|
|
#define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
|
|
|
|
#define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008
|
|
|
|
#define REG_A6XX_VFD_UNKNOWN_A009 0x0000a009
|
|
|
|
#define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
|
|
|
|
#define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
|
|
|
|
static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
|
|
#define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
|
|
#define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0
|
|
static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
|
|
}
|
|
#define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
|
|
#define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
|
|
#define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
|
|
static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val)
|
|
{
|
|
return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
|
|
}
|
|
#define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
|
|
#define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
|
|
static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
|
|
}
|
|
#define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000
|
|
#define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000
|
|
|
|
static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
|
|
#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
|
|
#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
|
|
static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
|
|
}
|
|
#define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
|
|
#define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
|
|
static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
|
|
|
|
#define REG_A6XX_SP_PRIMITIVE_CNTL 0x0000a802
|
|
#define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
|
|
#define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
|
|
static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
|
|
#define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
|
|
#define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
|
|
static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
|
|
}
|
|
#define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
|
|
#define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
|
|
static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
|
|
}
|
|
#define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
|
|
#define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
|
|
static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
|
|
}
|
|
#define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
|
|
#define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
|
|
static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
|
|
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
|
|
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
|
|
static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
|
|
}
|
|
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
|
|
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
|
|
static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
|
|
}
|
|
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
|
|
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
|
|
static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
|
|
}
|
|
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
|
|
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
|
|
static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
|
|
#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
|
|
#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
|
|
static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
|
|
#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
|
|
static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
|
|
#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
|
|
static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
|
|
}
|
|
#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
|
#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
|
|
static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
|
|
#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
|
|
#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b
|
|
|
|
#define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c
|
|
|
|
#define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d
|
|
|
|
#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
|
|
|
|
#define REG_A6XX_SP_VS_CONFIG 0x0000a823
|
|
#define A6XX_SP_VS_CONFIG_ENABLED 0x00000100
|
|
#define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00
|
|
#define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9
|
|
static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
|
|
}
|
|
#define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x01fe0000
|
|
#define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
|
|
static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
|
|
|
|
#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
|
|
#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
|
|
#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
|
|
static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
|
|
#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
|
|
static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
|
|
#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
|
|
static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
|
|
}
|
|
#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
|
#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20
|
|
static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000
|
|
#define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000
|
|
#define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000
|
|
|
|
#define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831
|
|
|
|
#define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834
|
|
|
|
#define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835
|
|
|
|
#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
|
|
|
|
#define REG_A6XX_SP_HS_CONFIG 0x0000a83b
|
|
#define A6XX_SP_HS_CONFIG_ENABLED 0x00000100
|
|
#define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00
|
|
#define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9
|
|
static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
|
|
}
|
|
#define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x01fe0000
|
|
#define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
|
|
static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
|
|
|
|
#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
|
|
#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
|
|
#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
|
|
static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
|
|
#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
|
|
static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
|
|
#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
|
|
static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
|
|
}
|
|
#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
|
#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20
|
|
static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000
|
|
#define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
|
|
#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
|
|
|
|
#define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c
|
|
|
|
#define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d
|
|
|
|
#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
|
|
|
|
#define REG_A6XX_SP_DS_CONFIG 0x0000a863
|
|
#define A6XX_SP_DS_CONFIG_ENABLED 0x00000100
|
|
#define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00
|
|
#define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9
|
|
static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
|
|
}
|
|
#define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x01fe0000
|
|
#define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
|
|
static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
|
|
|
|
#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
|
|
#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
|
|
#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
|
|
static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
|
|
#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
|
|
static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
|
|
#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
|
|
static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
|
|
}
|
|
#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
|
#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20
|
|
static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000
|
|
#define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000
|
|
#define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000
|
|
|
|
#define REG_A6XX_SP_GS_UNKNOWN_A871 0x0000a871
|
|
|
|
#define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d
|
|
|
|
#define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e
|
|
|
|
#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
|
|
|
|
#define REG_A6XX_SP_GS_CONFIG 0x0000a894
|
|
#define A6XX_SP_GS_CONFIG_ENABLED 0x00000100
|
|
#define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00
|
|
#define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9
|
|
static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
|
|
}
|
|
#define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x01fe0000
|
|
#define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
|
|
static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
|
|
|
|
#define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0
|
|
|
|
#define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1
|
|
|
|
#define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2
|
|
|
|
#define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3
|
|
|
|
#define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4
|
|
|
|
#define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5
|
|
|
|
#define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6
|
|
|
|
#define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7
|
|
|
|
#define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8
|
|
|
|
#define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9
|
|
|
|
#define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa
|
|
|
|
#define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab
|
|
|
|
#define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac
|
|
|
|
#define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad
|
|
|
|
#define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae
|
|
|
|
#define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af
|
|
|
|
#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
|
|
#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
|
|
#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
|
|
static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
|
|
#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
|
|
static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
|
|
#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
|
|
static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
|
|
}
|
|
#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
|
#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
|
|
static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
|
|
#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
|
|
#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_A982 0x0000a982
|
|
|
|
#define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983
|
|
|
|
#define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984
|
|
|
|
#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
|
|
#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
|
|
#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
|
|
#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
|
|
|
|
#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
|
|
#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
|
|
#define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
|
|
#define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004
|
|
#define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008
|
|
#define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010
|
|
#define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020
|
|
#define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040
|
|
#define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080
|
|
|
|
#define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0
|
|
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
|
|
}
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4
|
|
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
|
|
}
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8
|
|
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
|
|
}
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12
|
|
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
|
|
}
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16
|
|
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
|
|
}
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20
|
|
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
|
|
}
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24
|
|
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
|
|
}
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000
|
|
#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28
|
|
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c
|
|
#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00
|
|
#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8
|
|
static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
|
|
#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
|
|
#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
|
|
static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
|
|
}
|
|
|
|
static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
|
|
#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
|
|
#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_A99E 0x0000a99e
|
|
|
|
#define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
|
|
|
|
#define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0
|
|
|
|
#define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1
|
|
|
|
#define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2
|
|
|
|
#define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3
|
|
|
|
#define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4
|
|
|
|
#define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5
|
|
|
|
#define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6
|
|
|
|
#define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7
|
|
|
|
static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
|
|
|
|
static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
|
|
#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
|
|
#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
|
|
static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
|
|
}
|
|
#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
|
|
|
|
#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
|
|
#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
|
|
#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
|
|
static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
|
|
#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
|
|
static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
|
}
|
|
#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
|
|
#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
|
|
static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
|
|
}
|
|
#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
|
|
#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
|
|
static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
|
{
|
|
return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
|
|
}
|
|
#define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000
|
|
#define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000
|
|
#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
|
|
|
|
#define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4
|
|
|
|
#define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5
|
|
|
|
#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00
|
|
|
|
#define REG_A6XX_SP_FS_CONFIG 0x0000ab04
|
|
#define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
|
|
#define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
|
|
#define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
|
|
static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
|
|
}
|
|
#define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x01fe0000
|
|
#define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
|
|
static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_AB20 0x0000ab20
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_ACC0 0x0000acc0
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
|
|
|
|
#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
|
|
#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
|
|
#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
|
|
#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
|
|
static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
|
|
}
|
|
#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
|
|
|
|
#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302
|
|
|
|
#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303
|
|
|
|
#define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304
|
|
|
|
#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
|
|
|
|
#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
|
|
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
|
|
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
|
|
static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
|
|
{
|
|
return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
|
|
}
|
|
#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
|
|
#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
|
|
static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
|
|
{
|
|
return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
|
|
}
|
|
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
|
|
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
|
|
static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
|
|
}
|
|
#define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
|
|
#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
|
|
|
|
#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
|
|
#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
|
|
#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
|
|
static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
|
|
}
|
|
#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
|
|
#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
|
|
static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
|
|
|
|
#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
|
|
|
|
#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
|
|
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00
|
|
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
|
|
static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
|
|
|
|
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_B600 0x0000b600
|
|
|
|
#define REG_A6XX_SP_UNKNOWN_B605 0x0000b605
|
|
|
|
#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
|
|
#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
|
|
#define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
|
|
#define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
|
|
#define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
|
|
#define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
|
|
#define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
|
|
#define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
|
|
#define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980
|
|
|
|
#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
|
|
|
|
#define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
|
|
#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
|
|
#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
|
|
}
|
|
#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
|
|
#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
|
|
static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
|
|
}
|
|
#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
|
|
#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
|
|
static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
|
|
#define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
|
|
#define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
|
|
#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
|
|
#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
|
|
static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
|
|
}
|
|
#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
|
|
#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
|
|
static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
|
|
|
|
#define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
|
|
#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
|
|
#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
|
|
}
|
|
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
|
|
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
|
|
}
|
|
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
|
|
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
|
|
}
|
|
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
|
|
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991
|
|
#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
|
|
#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992
|
|
#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
|
|
#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993
|
|
#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
|
|
#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994
|
|
#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
|
|
#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995
|
|
#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
|
|
#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996
|
|
#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
|
|
#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
|
|
#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
|
|
#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
|
|
}
|
|
#define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
|
|
#define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
|
|
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
|
|
}
|
|
#define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
|
|
#define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
|
|
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
|
|
}
|
|
#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
|
|
#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
|
|
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
|
|
|
|
#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
|
|
|
|
#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
|
|
|
|
#define REG_A6XX_HLSQ_UPDATE_CNTL 0x0000bb08
|
|
|
|
#define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
|
|
#define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
|
|
#define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
|
|
static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
|
|
{
|
|
return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_HLSQ_UNKNOWN_BB11 0x0000bb11
|
|
|
|
#define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
|
|
|
|
#define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
|
|
|
|
#define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
|
|
|
|
#define REG_A6XX_TEX_SAMP_0 0x00000000
|
|
#define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
|
|
#define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
|
|
#define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1
|
|
static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
|
|
{
|
|
return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
|
|
}
|
|
#define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
|
|
#define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3
|
|
static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
|
|
{
|
|
return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
|
|
}
|
|
#define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
|
|
#define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5
|
|
static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
|
|
{
|
|
return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
|
|
}
|
|
#define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
|
|
#define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8
|
|
static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
|
|
{
|
|
return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
|
|
}
|
|
#define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
|
|
#define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11
|
|
static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
|
|
{
|
|
return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
|
|
}
|
|
#define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
|
|
#define A6XX_TEX_SAMP_0_ANISO__SHIFT 14
|
|
static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
|
|
{
|
|
return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
|
|
}
|
|
#define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
|
|
#define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
|
|
static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
|
|
{
|
|
return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_SAMP_1 0x00000001
|
|
#define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
|
|
#define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
|
|
static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
|
|
{
|
|
return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
|
|
}
|
|
#define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
|
|
#define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
|
|
#define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
|
|
#define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
|
|
#define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
|
|
static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
|
|
{
|
|
return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
|
|
}
|
|
#define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
|
|
#define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
|
|
static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
|
|
{
|
|
return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_SAMP_2 0x00000002
|
|
#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
|
|
#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
|
|
static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_SAMP_3 0x00000003
|
|
|
|
#define REG_A6XX_TEX_CONST_0 0x00000000
|
|
#define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
|
|
#define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
|
|
static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_0_SRGB 0x00000004
|
|
#define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
|
|
#define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4
|
|
static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
|
|
#define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
|
|
static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
|
|
#define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
|
|
static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
|
|
#define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13
|
|
static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
|
|
#define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16
|
|
static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
|
|
#define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
|
|
static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
|
|
#define A6XX_TEX_CONST_0_FMT__SHIFT 22
|
|
static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000
|
|
#define A6XX_TEX_CONST_0_SWAP__SHIFT 30
|
|
static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_CONST_1 0x00000001
|
|
#define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
|
|
#define A6XX_TEX_CONST_1_WIDTH__SHIFT 0
|
|
static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
|
|
#define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15
|
|
static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_CONST_2 0x00000002
|
|
#define A6XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
|
|
#define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
|
|
static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
|
|
#define A6XX_TEX_CONST_2_PITCH__SHIFT 7
|
|
static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000
|
|
#define A6XX_TEX_CONST_2_TYPE__SHIFT 29
|
|
static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_CONST_3 0x00000003
|
|
#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
|
|
#define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
|
|
static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
|
|
{
|
|
return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_3_FLAG 0x10000000
|
|
|
|
#define REG_A6XX_TEX_CONST_4 0x00000004
|
|
#define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
|
|
#define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5
|
|
static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_CONST_5 0x00000005
|
|
#define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
|
|
#define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0
|
|
static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
|
|
}
|
|
#define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
|
|
#define A6XX_TEX_CONST_5_DEPTH__SHIFT 17
|
|
static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_CONST_6 0x00000006
|
|
|
|
#define REG_A6XX_TEX_CONST_7 0x00000007
|
|
#define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0
|
|
#define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5
|
|
static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
|
|
{
|
|
return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_CONST_8 0x00000008
|
|
#define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff
|
|
#define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0
|
|
static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_TEX_CONST_9 0x00000009
|
|
|
|
#define REG_A6XX_TEX_CONST_10 0x0000000a
|
|
|
|
#define REG_A6XX_TEX_CONST_11 0x0000000b
|
|
|
|
#define REG_A6XX_TEX_CONST_12 0x0000000c
|
|
|
|
#define REG_A6XX_TEX_CONST_13 0x0000000d
|
|
|
|
#define REG_A6XX_TEX_CONST_14 0x0000000e
|
|
|
|
#define REG_A6XX_TEX_CONST_15 0x0000000f
|
|
|
|
#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
|
|
|
|
#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
|
|
|
|
#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
|
|
|
|
#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
|
|
}
|
|
|
|
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
|
|
{
|
|
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
|
|
}
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
|
|
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
|
|
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
|
|
{
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return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
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}
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
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static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
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{
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return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
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}
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
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static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
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{
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return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
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}
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
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static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
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{
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return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
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}
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
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static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
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{
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return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
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}
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
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static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
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{
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return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
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}
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
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#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
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static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
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{
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return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
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}
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#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f
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#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
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#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
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#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
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#endif /* A6XX_XML */
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