forked from Minki/linux
aead88bd0e
Some of the platforms like zynqmp ultrascale+ has a separate clock gate for the rx clock. Add an optional rx_clk so that the clock can be enabled. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
47 lines
1.8 KiB
Plaintext
47 lines
1.8 KiB
Plaintext
* Cadence MACB/GEM Ethernet controller
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Required properties:
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- compatible: Should be "cdns,[<chip>-]{macb|gem}"
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Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
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Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP
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available on sama5d3 SoCs.
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Use "cdns,np4-macb" for NP4 SoC devices.
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Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
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Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
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the Cadence GEM, or the generic form: "cdns,gem".
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Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
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Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
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Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
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Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
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Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
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Or the generic form: "cdns,emac".
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- reg: Address and length of the register set for the device
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- interrupts: Should contain macb interrupt
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- phy-mode: See ethernet.txt file in the same directory.
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- clock-names: Tuple listing input clock names.
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Required elements: 'pclk', 'hclk'
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Optional elements: 'tx_clk'
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Optional elements: 'rx_clk' applies to cdns,zynqmp-gem
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- clocks: Phandles to input clocks.
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Optional properties for PHY child node:
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- reset-gpios : Should specify the gpio for phy reset
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- magic-packet : If present, indicates that the hardware supports waking
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up via magic packet.
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Examples:
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macb0: ethernet@fffc4000 {
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compatible = "cdns,at32ap7000-macb";
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reg = <0xfffc4000 0x4000>;
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interrupts = <21>;
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phy-mode = "rmii";
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local-mac-address = [3a 0e 03 04 05 06];
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clock-names = "pclk", "hclk", "tx_clk";
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clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
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ethernet-phy@1 {
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reg = <0x1>;
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reset-gpios = <&pioE 6 1>;
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};
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};
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