forked from Minki/linux
2d7f5c48c0
Also remove the dependency on ARCv2, to increase compile coverage for !ARCV2 builds Acked-by: Daniel Lezcano <daniel.lezcnao@linaro.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
507 lines
14 KiB
C
507 lines
14 KiB
C
/*
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* AXS101/AXS103 Software Development Platform
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*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <linux/libfdt.h>
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#include <asm/asm-offsets.h>
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#include <asm/io.h>
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#include <asm/mach_desc.h>
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#include <soc/arc/mcip.h>
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#define AXS_MB_CGU 0xE0010000
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#define AXS_MB_CREG 0xE0011000
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#define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214)
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#define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220)
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#define CREG_MB_VER (AXS_MB_CREG + 0x230)
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#define CREG_MB_CONFIG (AXS_MB_CREG + 0x234)
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#define AXC001_CREG 0xF0001000
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#define AXC001_GPIO_INTC 0xF0003000
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static void __init axs10x_enable_gpio_intc_wire(void)
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{
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/*
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* Peripherals on CPU Card and Mother Board are wired to cpu intc via
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* intermediate DW APB GPIO blocks (mainly for debouncing)
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*
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* ---------------------
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* | snps,arc700-intc |
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* ---------------------
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* | #7 | #15
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* ------------------- -------------------
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* | snps,dw-apb-gpio | | snps,dw-apb-gpio |
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* ------------------- -------------------
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* | #12 |
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* | [ Debug UART on cpu card ]
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* |
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* ------------------------
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* | snps,dw-apb-intc (MB)|
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* ------------------------
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* | | | |
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* [eth] [uart] [... other perip on Main Board]
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*
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* Current implementation of "irq-dw-apb-ictl" driver doesn't work well
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* with stacked INTCs. In particular problem happens if its master INTC
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* not yet instantiated. See discussion here -
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* https://lkml.org/lkml/2015/3/4/755
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*
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* So setup the first gpio block as a passive pass thru and hide it from
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* DT hardware topology - connect MB intc directly to cpu intc
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* The GPIO "wire" needs to be init nevertheless (here)
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*
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* One side adv is that peripheral interrupt handling avoids one nested
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* intc ISR hop
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*/
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#define GPIO_INTEN (AXC001_GPIO_INTC + 0x30)
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#define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34)
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#define GPIO_INTTYPE_LEVEL (AXC001_GPIO_INTC + 0x38)
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#define GPIO_INT_POLARITY (AXC001_GPIO_INTC + 0x3c)
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#define MB_TO_GPIO_IRQ 12
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iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
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iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
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iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
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iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
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}
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static inline void __init
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write_cgu_reg(uint32_t value, void __iomem *reg, void __iomem *lock_reg)
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{
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unsigned int loops = 128 * 1024, ctr;
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iowrite32(value, reg);
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ctr = loops;
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while (((ioread32(lock_reg) & 1) == 1) && ctr--) /* wait for unlock */
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cpu_relax();
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ctr = loops;
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while (((ioread32(lock_reg) & 1) == 0) && ctr--) /* wait for re-lock */
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cpu_relax();
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}
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static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
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{
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union ver {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:11, y:12, m:4, d:5;
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#else
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unsigned int d:5, m:4, y:12, pad:11;
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#endif
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};
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unsigned int val;
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} board;
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board.val = ioread32((void __iomem *)creg);
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pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
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board.y);
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}
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static void __init axs10x_early_init(void)
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{
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int mb_rev;
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char mb[32];
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/* Determine motherboard version */
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if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
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mb_rev = 3; /* HT-3 (rev3.0) */
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else
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mb_rev = 2; /* HT-2 (rev2.0) */
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axs10x_enable_gpio_intc_wire();
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scnprintf(mb, 32, "MainBoard v%d", mb_rev);
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axs10x_print_board_ver(CREG_MB_VER, mb);
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}
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#ifdef CONFIG_AXS101
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#define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20)
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#define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60)
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#define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34)
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#define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74)
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#define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
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#define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120)
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/*
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* Set up System Memory Map for ARC cpu / peripherals controllers
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*
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* Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
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* of which maps to a corresponding 256MB aperture in Target slave memory map.
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*
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* e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
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* (0x0000_0000) of DDR Port 0 (slave #1)
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*
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* Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
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* which has master/slaves on both ends.
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* e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
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* (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
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* MB AXI Tunnel Master, which also has a mem map setup
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*
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* In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
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* to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
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*/
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struct aperture {
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unsigned int slave_sel:4, slave_off:4, pad:24;
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};
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/* CPU Card target slaves */
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#define AXC001_SLV_NONE 0
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#define AXC001_SLV_DDR_PORT0 1
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#define AXC001_SLV_SRAM 2
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#define AXC001_SLV_AXI_TUNNEL 3
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#define AXC001_SLV_AXI2APB 6
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#define AXC001_SLV_DDR_PORT1 7
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/* MB AXI Target slaves */
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#define AXS_MB_SLV_NONE 0
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#define AXS_MB_SLV_AXI_TUNNEL_CPU 1
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#define AXS_MB_SLV_AXI_TUNNEL_HAPS 2
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#define AXS_MB_SLV_SRAM 3
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#define AXS_MB_SLV_CONTROL 4
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/* MB AXI masters */
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#define AXS_MB_MST_TUNNEL_CPU 0
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#define AXS_MB_MST_USB_OHCI 10
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/*
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* memmap for ARC core on CPU Card
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*/
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static const struct aperture axc001_memmap[16] = {
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{AXC001_SLV_AXI_TUNNEL, 0x0},
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{AXC001_SLV_AXI_TUNNEL, 0x1},
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{AXC001_SLV_SRAM, 0x0}, /* 0x2000_0000: Local SRAM */
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_DDR_PORT0, 0x0}, /* 0x8000_0000: DDR 0..256M */
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{AXC001_SLV_DDR_PORT0, 0x1}, /* 0x9000_0000: DDR 256..512M */
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{AXC001_SLV_DDR_PORT0, 0x2},
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{AXC001_SLV_DDR_PORT0, 0x3},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_AXI_TUNNEL, 0xD},
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{AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */
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{AXC001_SLV_AXI2APB, 0x0}, /* CPU Card local CREG, CGU... */
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};
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/*
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* memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
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* GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
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*/
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static const struct aperture axc001_axi_tunnel_memmap[16] = {
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{AXC001_SLV_AXI_TUNNEL, 0x0},
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{AXC001_SLV_AXI_TUNNEL, 0x1},
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{AXC001_SLV_SRAM, 0x0},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_DDR_PORT1, 0x0},
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{AXC001_SLV_DDR_PORT1, 0x1},
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{AXC001_SLV_DDR_PORT1, 0x2},
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{AXC001_SLV_DDR_PORT1, 0x3},
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{AXC001_SLV_NONE, 0x0},
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{AXC001_SLV_AXI_TUNNEL, 0xD},
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{AXC001_SLV_AXI_TUNNEL, 0xE},
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{AXC001_SLV_AXI2APB, 0x0},
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};
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/*
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* memmap for MB AXI Masters
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* Same mem map for all perip controllers as well as MB AXI Tunnel Master
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*/
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static const struct aperture axs_mb_memmap[16] = {
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{AXS_MB_SLV_SRAM, 0x0},
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{AXS_MB_SLV_SRAM, 0x0},
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{AXS_MB_SLV_NONE, 0x0},
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{AXS_MB_SLV_NONE, 0x0},
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{AXS_MB_SLV_NONE, 0x0},
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{AXS_MB_SLV_NONE, 0x0},
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{AXS_MB_SLV_NONE, 0x0},
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{AXS_MB_SLV_NONE, 0x0},
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{AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8}, /* DDR on CPU Card */
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{AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9}, /* DDR on CPU Card */
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{AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA},
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{AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB},
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{AXS_MB_SLV_NONE, 0x0},
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{AXS_MB_SLV_AXI_TUNNEL_HAPS, 0xD},
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{AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */
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{AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF},
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};
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static noinline void __init
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axs101_set_memmap(void __iomem *base, const struct aperture map[16])
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{
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unsigned int slave_select, slave_offset;
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int i;
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slave_select = slave_offset = 0;
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for (i = 0; i < 8; i++) {
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slave_select |= map[i].slave_sel << (i << 2);
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slave_offset |= map[i].slave_off << (i << 2);
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}
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iowrite32(slave_select, base + 0x0); /* SLV0 */
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iowrite32(slave_offset, base + 0x8); /* OFFSET0 */
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slave_select = slave_offset = 0;
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for (i = 0; i < 8; i++) {
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slave_select |= map[i+8].slave_sel << (i << 2);
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slave_offset |= map[i+8].slave_off << (i << 2);
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}
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iowrite32(slave_select, base + 0x4); /* SLV1 */
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iowrite32(slave_offset, base + 0xC); /* OFFSET1 */
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}
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static void __init axs101_early_init(void)
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{
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int i;
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/* ARC 770D memory view */
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axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
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iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
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/* AXI tunnel memory map (incoming traffic from MB into CPU Card */
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axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
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axc001_axi_tunnel_memmap);
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iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
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/* MB peripherals memory map */
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for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
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axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
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axs_mb_memmap);
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iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */
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/* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
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iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
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/* Set up the MB interrupt system: mux interrupts to GPIO7) */
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iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
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/* reset ethernet and ULPI interfaces */
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iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
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/* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
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iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
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axs10x_early_init();
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}
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#endif /* CONFIG_AXS101 */
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#ifdef CONFIG_AXS103
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#define AXC003_CGU 0xF0000000
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#define AXC003_CREG 0xF0001000
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#define AXC003_MST_AXI_TUNNEL 0
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#define AXC003_MST_HS38 1
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#define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440)
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#define CREG_CPU_GPIO_UART_MUX (AXC003_CREG + 0x480)
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#define CREG_CPU_TUN_IO_CTRL (AXC003_CREG + 0x494)
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union pll_reg {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:17, noupd:1, bypass:1, edge:1, high:6, low:6;
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#else
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unsigned int low:6, high:6, edge:1, bypass:1, noupd:1, pad:17;
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#endif
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};
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unsigned int val;
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};
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static unsigned int __init axs103_get_freq(void)
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{
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union pll_reg idiv, fbdiv, odiv;
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unsigned int f = 33333333;
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idiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 0);
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fbdiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 4);
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odiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 8);
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if (idiv.bypass != 1)
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f = f / (idiv.low + idiv.high);
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if (fbdiv.bypass != 1)
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f = f * (fbdiv.low + fbdiv.high);
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if (odiv.bypass != 1)
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f = f / (odiv.low + odiv.high);
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f = (f + 500000) / 1000000; /* Rounding */
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return f;
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}
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static inline unsigned int __init encode_div(unsigned int id, int upd)
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{
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union pll_reg div;
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div.val = 0;
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div.noupd = !upd;
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div.bypass = id == 1 ? 1 : 0;
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div.edge = (id%2 == 0) ? 0 : 1; /* 0 = rising */
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div.low = (id%2 == 0) ? id >> 1 : (id >> 1)+1;
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div.high = id >> 1;
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return div.val;
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}
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noinline static void __init
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axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
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{
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write_cgu_reg(encode_div(id, 0),
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(void __iomem *)AXC003_CGU + 0x80 + 0,
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(void __iomem *)AXC003_CGU + 0x110);
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write_cgu_reg(encode_div(fd, 0),
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(void __iomem *)AXC003_CGU + 0x80 + 4,
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(void __iomem *)AXC003_CGU + 0x110);
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write_cgu_reg(encode_div(od, 1),
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(void __iomem *)AXC003_CGU + 0x80 + 8,
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(void __iomem *)AXC003_CGU + 0x110);
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}
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static void __init axs103_early_init(void)
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{
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int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
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const struct fdt_property *prop = fdt_get_property(initial_boot_params,
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offset,
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"clock-frequency",
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NULL);
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u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq;
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/*
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* AXS103 configurations for SMP/QUAD configurations share device tree
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* which defaults to 90 MHz. However recent failures of Quad config
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* revealed P&R timing violations so clamp it down to safe 50 MHz
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* Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
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*
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* This hack is really hacky as of now. Fix it properly by getting the
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* number of cores as return value of platform's early SMP callback
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*/
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#ifdef CONFIG_ARC_MCIP
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unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
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if (num_cores > 2)
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freq = 50;
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#endif
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switch (freq) {
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case 33:
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axs103_set_freq(1, 1, 1);
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break;
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case 50:
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axs103_set_freq(1, 30, 20);
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break;
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case 75:
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axs103_set_freq(2, 45, 10);
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break;
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case 90:
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axs103_set_freq(2, 54, 10);
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break;
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case 100:
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axs103_set_freq(1, 30, 10);
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break;
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case 125:
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axs103_set_freq(2, 45, 6);
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break;
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default:
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/*
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|
* In this case, core_frequency derived from
|
|
* DT "clock-frequency" might not match with board value.
|
|
* Hence update it to match the board value.
|
|
*/
|
|
freq = axs103_get_freq();
|
|
break;
|
|
}
|
|
|
|
pr_info("Freq is %dMHz\n", freq);
|
|
|
|
/* Patching .dtb in-place with new core clock value */
|
|
if (freq != orig ) {
|
|
freq = cpu_to_be32(freq * 1000000);
|
|
fdt_setprop_inplace(initial_boot_params, offset,
|
|
"clock-frequency", &freq, sizeof(freq));
|
|
}
|
|
|
|
/* Memory maps already config in pre-bootloader */
|
|
|
|
/* set GPIO mux to UART */
|
|
iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
|
|
|
|
iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
|
|
(void __iomem *) CREG_CPU_TUN_IO_CTRL);
|
|
|
|
/* Set up the AXS_MB interrupt system.*/
|
|
iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
|
|
+ (AXC003_MST_HS38 << 2)));
|
|
|
|
/* connect ICTL - Main Board with GPIO line */
|
|
iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
|
|
|
|
axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
|
|
|
|
axs10x_early_init();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_AXS101
|
|
|
|
static const char *axs101_compat[] __initconst = {
|
|
"snps,axs101",
|
|
NULL,
|
|
};
|
|
|
|
MACHINE_START(AXS101, "axs101")
|
|
.dt_compat = axs101_compat,
|
|
.init_early = axs101_early_init,
|
|
MACHINE_END
|
|
|
|
#endif /* CONFIG_AXS101 */
|
|
|
|
#ifdef CONFIG_AXS103
|
|
|
|
static const char *axs103_compat[] __initconst = {
|
|
"snps,axs103",
|
|
NULL,
|
|
};
|
|
|
|
MACHINE_START(AXS103, "axs103")
|
|
.dt_compat = axs103_compat,
|
|
.init_early = axs103_early_init,
|
|
MACHINE_END
|
|
|
|
/*
|
|
* For the VDK OS-kit, to get the offset to pid and command fields
|
|
*/
|
|
char coware_swa_pid_offset[TASK_PID];
|
|
char coware_swa_comm_offset[TASK_COMM];
|
|
|
|
#endif /* CONFIG_AXS103 */
|