linux/drivers/gpu
Madhav Chauhan 166869b390 drm/i915/icl: Define PORT_CL_DW_10 register
This register used to power down individual lanes for
DDI/DSI ports. Bitfields to power up/down various
combinations of lanes are also added in this patch.

v2: Review comments from Jani N
    - Use override instead of "override" for bitfields
    - Define mask for override bitfield
    - Define PWR_DOWN_LN* macros shifted in place
v3: Correct PWR_DOWN_LN_MASK value (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530798591-2077-6-git-send-email-madhav.chauhan@intel.com
2018-07-06 12:14:16 +03:00
..
drm drm/i915/icl: Define PORT_CL_DW_10 register 2018-07-06 12:14:16 +03:00
host1x
ipu-v3 gpu: ipu-v3: prg: avoid possible array underflow 2018-03-15 17:52:08 +01:00
vga vga_switcheroo: Let HDA autosuspend on mux change 2018-03-13 22:58:49 +01:00
Makefile