3108e6ab21
This does two things to the FPGA IRQ controller in the versatile family: - Convert to MULTI_IRQ_HANDLER so we can drop the entry macro from the Integrator. The C IRQ handler was inspired from arch/arm/common/vic.c, recent bug discovered in this handler was accounted for. - Convert to using IRQ domains so we can get rid of the NO_IRQ mess and proceed with device tree and such stuff. As part of the exercise, bump all the low IRQ numbers on the Integrator PIC to start from 1 rather than 0, since IRQ 0 is now NO_IRQ. The Linux IRQ numbers are thus entirely decoupled from the hardware IRQ numbers in this controller. I was unable to split this patch. The main reason is the half-done conversion to device tree in Versatile. Tested on Integrator/AP and Integrator/CP. Cc: Grant Likely <grant.likely@secretlab.ca> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
/*
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* arch/arm/mach-integrator/include/mach/irqs.h
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*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Interrupt numbers
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*/
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#define IRQ_PIC_START 1
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#define IRQ_SOFTINT 1
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#define IRQ_UARTINT0 2
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#define IRQ_UARTINT1 3
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#define IRQ_KMIINT0 4
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#define IRQ_KMIINT1 5
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#define IRQ_TIMERINT0 6
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#define IRQ_TIMERINT1 7
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#define IRQ_TIMERINT2 8
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#define IRQ_RTCINT 9
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#define IRQ_AP_EXPINT0 10
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#define IRQ_AP_EXPINT1 11
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#define IRQ_AP_EXPINT2 12
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#define IRQ_AP_EXPINT3 13
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#define IRQ_AP_PCIINT0 14
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#define IRQ_AP_PCIINT1 15
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#define IRQ_AP_PCIINT2 16
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#define IRQ_AP_PCIINT3 17
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#define IRQ_AP_V3INT 18
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#define IRQ_AP_CPINT0 19
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#define IRQ_AP_CPINT1 20
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#define IRQ_AP_LBUSTIMEOUT 21
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#define IRQ_AP_APCINT 22
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#define IRQ_CP_CLCDCINT 23
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#define IRQ_CP_MMCIINT0 24
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#define IRQ_CP_MMCIINT1 25
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#define IRQ_CP_AACIINT 26
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#define IRQ_CP_CPPLDINT 27
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#define IRQ_CP_ETHINT 28
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#define IRQ_CP_TSPENINT 29
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#define IRQ_PIC_END 29
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#define IRQ_CIC_START 32
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#define IRQ_CM_SOFTINT 32
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#define IRQ_CM_COMMRX 33
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#define IRQ_CM_COMMTX 34
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#define IRQ_CIC_END 34
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/*
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* IntegratorCP only
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*/
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#define IRQ_SIC_START 35
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#define IRQ_SIC_CP_SOFTINT 35
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#define IRQ_SIC_CP_RI0 36
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#define IRQ_SIC_CP_RI1 37
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#define IRQ_SIC_CP_CARDIN 38
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#define IRQ_SIC_CP_LMINT0 39
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#define IRQ_SIC_CP_LMINT1 40
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#define IRQ_SIC_CP_LMINT2 41
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#define IRQ_SIC_CP_LMINT3 42
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#define IRQ_SIC_CP_LMINT4 43
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#define IRQ_SIC_CP_LMINT5 44
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#define IRQ_SIC_CP_LMINT6 45
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#define IRQ_SIC_CP_LMINT7 46
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#define IRQ_SIC_END 46
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#define NR_IRQS_INTEGRATOR_AP 34
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#define NR_IRQS_INTEGRATOR_CP 47
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