f2b0b25a37
In case of ARCv2 CPU there're could be following configurations
that affect cache handling for data exchanged with peripherals
via DMA:
[1] Only L1 cache exists
[2] Both L1 and L2 exist, but no IO coherency unit
[3] L1, L2 caches and IO coherency unit exist
Current implementation takes care of [1] and [2].
Moreover support of [2] is implemented with run-time check
for SLC existence which is not super optimal.
This patch introduces support of [3] and rework of DMA ops
usage. Instead of doing run-time check every time a particular
DMA op is executed we'll have 3 different implementations of
DMA ops and select appropriate one during init.
As for IOC support for it we need:
[a] Implement empty DMA ops because IOC takes care of cache
coherency with DMAed data
[b] Route dma_alloc_coherent() via dma_alloc_noncoherent()
This is required to make IOC work in first place and also
serves as optimization as LD/ST to coherent buffers can be
srviced from caches w/o going all the way to memory
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
[vgupta:
-Added some comments about IOC gains
-Marked dma ops as static,
-Massaged changelog a bit]
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
121 lines
3.3 KiB
C
121 lines
3.3 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* DMA Coherent API Notes
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*
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* I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
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* implemented by accessintg it using a kernel virtual address, with
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* Cache bit off in the TLB entry.
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*
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* The default DMA address == Phy address which is 0x8000_0000 based.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/dma-debug.h>
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#include <linux/export.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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/*
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* Helpers for Coherent DMA API.
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*/
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void *dma_alloc_noncoherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp)
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{
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void *paddr;
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/* This is linear addr (0x8000_0000 based) */
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paddr = alloc_pages_exact(size, gfp);
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if (!paddr)
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return NULL;
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/* This is bus address, platform dependent */
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*dma_handle = (dma_addr_t)paddr;
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return paddr;
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}
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EXPORT_SYMBOL(dma_alloc_noncoherent);
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void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle)
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{
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free_pages_exact((void *)dma_handle, size);
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}
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EXPORT_SYMBOL(dma_free_noncoherent);
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void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp)
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{
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void *paddr, *kvaddr;
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/*
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* IOC relies on all data (even coherent DMA data) being in cache
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* Thus allocate normal cached memory
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*
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* The gains with IOC are two pronged:
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* -For streaming data, elides needs for cache maintenance, saving
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* cycles in flush code, and bus bandwidth as all the lines of a
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* buffer need to be flushed out to memory
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* -For coherent data, Read/Write to buffers terminate early in cache
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* (vs. always going to memory - thus are faster)
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*/
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if (ioc_exists)
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return dma_alloc_noncoherent(dev, size, dma_handle, gfp);
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/* This is linear addr (0x8000_0000 based) */
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paddr = alloc_pages_exact(size, gfp);
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if (!paddr)
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return NULL;
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/* This is kernel Virtual address (0x7000_0000 based) */
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kvaddr = ioremap_nocache((unsigned long)paddr, size);
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if (kvaddr == NULL)
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return NULL;
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/* This is bus address, platform dependent */
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*dma_handle = (dma_addr_t)paddr;
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/*
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* Evict any existing L1 and/or L2 lines for the backing page
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* in case it was used earlier as a normal "cached" page.
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* Yeah this bit us - STAR 9000898266
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*
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* Although core does call flush_cache_vmap(), it gets kvaddr hence
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* can't be used to efficiently flush L1 and/or L2 which need paddr
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* Currently flush_cache_vmap nukes the L1 cache completely which
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* will be optimized as a separate commit
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*/
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dma_cache_wback_inv((unsigned long)paddr, size);
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return kvaddr;
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}
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EXPORT_SYMBOL(dma_alloc_coherent);
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void dma_free_coherent(struct device *dev, size_t size, void *kvaddr,
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dma_addr_t dma_handle)
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{
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if (ioc_exists)
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return dma_free_noncoherent(dev, size, kvaddr, dma_handle);
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iounmap((void __force __iomem *)kvaddr);
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free_pages_exact((void *)dma_handle, size);
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}
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EXPORT_SYMBOL(dma_free_coherent);
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/*
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* Helper for streaming DMA...
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*/
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void __arc_dma_cache_sync(unsigned long paddr, size_t size,
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enum dma_data_direction dir)
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{
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__inline_dma_cache_sync(paddr, size, dir);
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}
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EXPORT_SYMBOL(__arc_dma_cache_sync);
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