24b0e3e84f
The DDR controller need to be used by the IRQ controller to flush the write buffer of some devices before running the IRQ handler. It is also used by the PCI controller to setup the PCI memory windows. The current interface used to access the DDR controller doesn't provides any useful abstraction and simply rely on a shared global pointer. Replace this by a simple API to setup the PCI memory windows and use the write buffer flush independently of the SoC type. That remove the need for the shared global pointer, simplify the IRQ handler code. [ralf@linux-mips.org: Folded in Alban Bedel's follup fix.] Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9773/ Patchwork: http://patchwork.linux-mips.org/patch/10543/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
147 lines
2.9 KiB
C
147 lines
2.9 KiB
C
/*
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* Atheros AR71XX/AR724X/AR913X common definitions
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_ATH79_H
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#define __ASM_MACH_ATH79_H
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#include <linux/types.h>
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#include <linux/io.h>
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enum ath79_soc_type {
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ATH79_SOC_UNKNOWN,
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ATH79_SOC_AR7130,
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ATH79_SOC_AR7141,
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ATH79_SOC_AR7161,
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ATH79_SOC_AR7240,
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ATH79_SOC_AR7241,
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ATH79_SOC_AR7242,
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ATH79_SOC_AR9130,
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ATH79_SOC_AR9132,
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ATH79_SOC_AR9330,
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ATH79_SOC_AR9331,
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ATH79_SOC_AR9341,
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ATH79_SOC_AR9342,
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ATH79_SOC_AR9344,
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ATH79_SOC_QCA9556,
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ATH79_SOC_QCA9558,
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};
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extern enum ath79_soc_type ath79_soc;
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extern unsigned int ath79_soc_rev;
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static inline int soc_is_ar71xx(void)
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{
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return (ath79_soc == ATH79_SOC_AR7130 ||
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ath79_soc == ATH79_SOC_AR7141 ||
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ath79_soc == ATH79_SOC_AR7161);
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}
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static inline int soc_is_ar724x(void)
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{
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return (ath79_soc == ATH79_SOC_AR7240 ||
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ath79_soc == ATH79_SOC_AR7241 ||
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ath79_soc == ATH79_SOC_AR7242);
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}
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static inline int soc_is_ar7240(void)
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{
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return (ath79_soc == ATH79_SOC_AR7240);
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}
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static inline int soc_is_ar7241(void)
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{
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return (ath79_soc == ATH79_SOC_AR7241);
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}
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static inline int soc_is_ar7242(void)
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{
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return (ath79_soc == ATH79_SOC_AR7242);
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}
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static inline int soc_is_ar913x(void)
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{
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return (ath79_soc == ATH79_SOC_AR9130 ||
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ath79_soc == ATH79_SOC_AR9132);
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}
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static inline int soc_is_ar933x(void)
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{
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return (ath79_soc == ATH79_SOC_AR9330 ||
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ath79_soc == ATH79_SOC_AR9331);
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}
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static inline int soc_is_ar9341(void)
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{
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return (ath79_soc == ATH79_SOC_AR9341);
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}
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static inline int soc_is_ar9342(void)
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{
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return (ath79_soc == ATH79_SOC_AR9342);
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}
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static inline int soc_is_ar9344(void)
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{
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return (ath79_soc == ATH79_SOC_AR9344);
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}
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static inline int soc_is_ar934x(void)
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{
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return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
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}
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static inline int soc_is_qca9556(void)
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{
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return ath79_soc == ATH79_SOC_QCA9556;
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}
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static inline int soc_is_qca9558(void)
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{
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return ath79_soc == ATH79_SOC_QCA9558;
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}
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static inline int soc_is_qca955x(void)
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{
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return soc_is_qca9556() || soc_is_qca9558();
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}
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void ath79_ddr_set_pci_windows(void);
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extern void __iomem *ath79_pll_base;
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extern void __iomem *ath79_reset_base;
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static inline void ath79_pll_wr(unsigned reg, u32 val)
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{
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__raw_writel(val, ath79_pll_base + reg);
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}
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static inline u32 ath79_pll_rr(unsigned reg)
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{
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return __raw_readl(ath79_pll_base + reg);
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}
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static inline void ath79_reset_wr(unsigned reg, u32 val)
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{
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__raw_writel(val, ath79_reset_base + reg);
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}
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static inline u32 ath79_reset_rr(unsigned reg)
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{
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return __raw_readl(ath79_reset_base + reg);
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}
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void ath79_device_reset_set(u32 mask);
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void ath79_device_reset_clear(u32 mask);
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#endif /* __ASM_MACH_ATH79_H */
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