7dc56af526
Before we submit the first context to HW, we need to construct a valid image of the register state. This layout is defined by the HW and should match the layout generated by HW when it saves the context image. Asserting that this should be equivalent should help avoid any undefined behaviour and verify that we haven't missed anything important! Of course, having insisted that the initial register state within the LRC should match that returned by HW, we need to ensure that it does. v2: Drop the RELATIVE_MMIO flag from gen11, we ignore it for constructing the lrc image. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190924145950.3011-1-chris@chris-wilson.co.uk
56 lines
1.7 KiB
C
56 lines
1.7 KiB
C
/*
|
|
* SPDX-License-Identifier: MIT
|
|
*
|
|
* Copyright © 2014-2018 Intel Corporation
|
|
*/
|
|
|
|
#ifndef _INTEL_LRC_REG_H_
|
|
#define _INTEL_LRC_REG_H_
|
|
|
|
#include <linux/types.h>
|
|
|
|
/* GEN8 to GEN11 Reg State Context */
|
|
#define CTX_CONTEXT_CONTROL (0x02 + 1)
|
|
#define CTX_RING_HEAD (0x04 + 1)
|
|
#define CTX_RING_TAIL (0x06 + 1)
|
|
#define CTX_RING_BUFFER_START (0x08 + 1)
|
|
#define CTX_RING_BUFFER_CONTROL (0x0a + 1)
|
|
#define CTX_BB_STATE (0x10 + 1)
|
|
#define CTX_BB_PER_CTX_PTR (0x18 + 1)
|
|
#define CTX_PDP3_UDW (0x24 + 1)
|
|
#define CTX_PDP3_LDW (0x26 + 1)
|
|
#define CTX_PDP2_UDW (0x28 + 1)
|
|
#define CTX_PDP2_LDW (0x2a + 1)
|
|
#define CTX_PDP1_UDW (0x2c + 1)
|
|
#define CTX_PDP1_LDW (0x2e + 1)
|
|
#define CTX_PDP0_UDW (0x30 + 1)
|
|
#define CTX_PDP0_LDW (0x32 + 1)
|
|
#define CTX_R_PWR_CLK_STATE (0x42 + 1)
|
|
|
|
#define GEN9_CTX_RING_MI_MODE 0x54
|
|
|
|
/* GEN12+ Reg State Context */
|
|
#define GEN12_CTX_BB_PER_CTX_PTR (0x12 + 1)
|
|
|
|
#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
|
|
u32 *reg_state__ = (reg_state); \
|
|
const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \
|
|
(reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \
|
|
(reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \
|
|
} while (0)
|
|
|
|
#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
|
|
u32 *reg_state__ = (reg_state); \
|
|
const u64 addr__ = px_dma(ppgtt->pd); \
|
|
(reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \
|
|
(reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \
|
|
} while (0)
|
|
|
|
#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
|
|
#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
|
|
#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19
|
|
#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A
|
|
#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0xD
|
|
|
|
#endif /* _INTEL_LRC_REG_H_ */
|