forked from Minki/linux
9026e0d122
The Allwinner A10 and subsequent SoCs share the same display pipeline, with variations in the number of controllers (1 or 2), or the presence or not of some output (HDMI, TV, VGA) or not. Add a driver with a limited set of features for now, and we will hopefully support all of them eventually Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
161 lines
3.6 KiB
C
161 lines
3.6 KiB
C
/*
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* Copyright (C) 2016 Free Electrons
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* Copyright (C) 2016 NextThing Co
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "sun4i_tcon.h"
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struct sun4i_dclk {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw)
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{
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return container_of(hw, struct sun4i_dclk, hw);
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}
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static void sun4i_dclk_disable(struct clk_hw *hw)
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{
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struct sun4i_dclk *dclk = hw_to_dclk(hw);
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regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
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BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0);
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}
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static int sun4i_dclk_enable(struct clk_hw *hw)
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{
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struct sun4i_dclk *dclk = hw_to_dclk(hw);
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return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
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BIT(SUN4I_TCON0_DCLK_GATE_BIT),
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BIT(SUN4I_TCON0_DCLK_GATE_BIT));
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}
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static int sun4i_dclk_is_enabled(struct clk_hw *hw)
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{
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struct sun4i_dclk *dclk = hw_to_dclk(hw);
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u32 val;
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regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
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return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT);
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}
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static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sun4i_dclk *dclk = hw_to_dclk(hw);
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u32 val;
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regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
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val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
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val &= SUN4I_TCON0_DCLK_DIV_WIDTH;
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if (!val)
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val = 1;
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return parent_rate / val;
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}
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static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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return *parent_rate / DIV_ROUND_CLOSEST(*parent_rate, rate);
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}
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static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sun4i_dclk *dclk = hw_to_dclk(hw);
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int div = DIV_ROUND_CLOSEST(parent_rate, rate);
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return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
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GENMASK(6, 0), div);
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}
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static int sun4i_dclk_get_phase(struct clk_hw *hw)
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{
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struct sun4i_dclk *dclk = hw_to_dclk(hw);
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u32 val;
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regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val);
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val >>= 28;
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val &= 3;
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return val * 120;
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}
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static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
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{
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struct sun4i_dclk *dclk = hw_to_dclk(hw);
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regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
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GENMASK(29, 28),
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degrees / 120);
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return 0;
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}
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static const struct clk_ops sun4i_dclk_ops = {
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.disable = sun4i_dclk_disable,
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.enable = sun4i_dclk_enable,
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.is_enabled = sun4i_dclk_is_enabled,
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.recalc_rate = sun4i_dclk_recalc_rate,
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.round_rate = sun4i_dclk_round_rate,
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.set_rate = sun4i_dclk_set_rate,
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.get_phase = sun4i_dclk_get_phase,
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.set_phase = sun4i_dclk_set_phase,
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};
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int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
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{
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const char *clk_name, *parent_name;
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struct clk_init_data init;
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struct sun4i_dclk *dclk;
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parent_name = __clk_get_name(tcon->sclk0);
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of_property_read_string_index(dev->of_node, "clock-output-names", 0,
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&clk_name);
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dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
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if (!dclk)
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return -ENOMEM;
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init.name = clk_name;
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init.ops = &sun4i_dclk_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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dclk->regmap = tcon->regs;
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dclk->hw.init = &init;
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tcon->dclk = clk_register(dev, &dclk->hw);
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if (IS_ERR(tcon->dclk))
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return PTR_ERR(tcon->dclk);
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return 0;
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}
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EXPORT_SYMBOL(sun4i_dclk_create);
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int sun4i_dclk_free(struct sun4i_tcon *tcon)
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{
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clk_unregister(tcon->dclk);
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return 0;
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}
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EXPORT_SYMBOL(sun4i_dclk_free);
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