forked from Minki/linux
ffdb1e369a
For Intel 7260 modem, it is needed for host side to send zero packet if the BULK OUT size is equal to USB endpoint max packet length. Otherwise, modem side may still wait for more data and cannot give response to host side. Signed-off-by: Konrad Leszczynski <konrad.leszczynski@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/*
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*
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* Includes for cdc-acm.c
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*
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* Mainly take from usbnet's cdc-ether part
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*
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*/
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/*
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* CMSPAR, some architectures can't have space and mark parity.
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*/
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#ifndef CMSPAR
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#define CMSPAR 0
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#endif
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/*
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* Major and minor numbers.
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*/
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#define ACM_TTY_MAJOR 166
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#define ACM_TTY_MINORS 256
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/*
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* Requests.
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*/
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#define USB_RT_ACM (USB_TYPE_CLASS | USB_RECIP_INTERFACE)
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/*
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* Output control lines.
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*/
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#define ACM_CTRL_DTR 0x01
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#define ACM_CTRL_RTS 0x02
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/*
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* Input control lines and line errors.
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*/
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#define ACM_CTRL_DCD 0x01
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#define ACM_CTRL_DSR 0x02
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#define ACM_CTRL_BRK 0x04
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#define ACM_CTRL_RI 0x08
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#define ACM_CTRL_FRAMING 0x10
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#define ACM_CTRL_PARITY 0x20
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#define ACM_CTRL_OVERRUN 0x40
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/*
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* Internal driver structures.
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*/
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/*
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* The only reason to have several buffers is to accommodate assumptions
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* in line disciplines. They ask for empty space amount, receive our URB size,
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* and proceed to issue several 1-character writes, assuming they will fit.
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* The very first write takes a complete URB. Fortunately, this only happens
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* when processing onlcr, so we only need 2 buffers. These values must be
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* powers of 2.
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*/
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#define ACM_NW 16
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#define ACM_NR 16
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struct acm_wb {
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unsigned char *buf;
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dma_addr_t dmah;
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int len;
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int use;
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struct urb *urb;
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struct acm *instance;
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};
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struct acm_rb {
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int size;
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unsigned char *base;
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dma_addr_t dma;
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int index;
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struct acm *instance;
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};
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struct acm {
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struct usb_device *dev; /* the corresponding usb device */
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struct usb_interface *control; /* control interface */
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struct usb_interface *data; /* data interface */
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struct tty_port port; /* our tty port data */
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struct urb *ctrlurb; /* urbs */
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u8 *ctrl_buffer; /* buffers of urbs */
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dma_addr_t ctrl_dma; /* dma handles of buffers */
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u8 *country_codes; /* country codes from device */
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unsigned int country_code_size; /* size of this buffer */
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unsigned int country_rel_date; /* release date of version */
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struct acm_wb wb[ACM_NW];
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unsigned long read_urbs_free;
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struct urb *read_urbs[ACM_NR];
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struct acm_rb read_buffers[ACM_NR];
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int rx_buflimit;
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int rx_endpoint;
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spinlock_t read_lock;
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int write_used; /* number of non-empty write buffers */
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int transmitting;
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spinlock_t write_lock;
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struct mutex mutex;
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bool disconnected;
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struct usb_cdc_line_coding line; /* bits, stop, parity */
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struct work_struct work; /* work queue entry for line discipline waking up */
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unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */
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unsigned int ctrlout; /* output control lines (DTR, RTS) */
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struct async_icount iocount; /* counters for control line changes */
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struct async_icount oldcount; /* for comparison of counter */
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wait_queue_head_t wioctl; /* for ioctl */
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unsigned int writesize; /* max packet size for the output bulk endpoint */
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unsigned int readsize,ctrlsize; /* buffer sizes for freeing */
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unsigned int minor; /* acm minor number */
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unsigned char clocal; /* termios CLOCAL */
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unsigned int ctrl_caps; /* control capabilities from the class specific header */
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unsigned int susp_count; /* number of suspended interfaces */
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unsigned int combined_interfaces:1; /* control and data collapsed */
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unsigned int is_int_ep:1; /* interrupt endpoints contrary to spec used */
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unsigned int throttled:1; /* actually throttled */
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unsigned int throttle_req:1; /* throttle requested */
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u8 bInterval;
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struct usb_anchor delayed; /* writes queued for a device about to be woken */
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unsigned long quirks;
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};
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#define CDC_DATA_INTERFACE_TYPE 0x0a
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/* constants describing various quirks and errors */
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#define NO_UNION_NORMAL BIT(0)
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#define SINGLE_RX_URB BIT(1)
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#define NO_CAP_LINE BIT(2)
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#define NO_DATA_INTERFACE BIT(4)
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#define IGNORE_DEVICE BIT(5)
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#define QUIRK_CONTROL_LINE_STATE BIT(6)
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#define CLEAR_HALT_CONDITIONS BIT(7)
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#define SEND_ZERO_PACKET BIT(8)
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