forked from Minki/linux
2cb3427642
This change provides a simpler implementation of mte_get_mem_tag(), mte_get_random_tag(), and mte_set_mem_tag_range(). Simplifications include removing system_supports_mte() checks as these functions are onlye called from KASAN runtime that had already checked system_supports_mte(). Besides that, size and address alignment checks are removed from mte_set_mem_tag_range(), as KASAN now does those. This change also moves these functions into the asm/mte-kasan.h header and implements mte_set_mem_tag_range() via inline assembly to avoid unnecessary functions calls. [vincenzo.frascino@arm.com: fix warning in mte_get_random_tag()] Link: https://lkml.kernel.org/r/20210211152208.23811-1-vincenzo.frascino@arm.com Link: https://lkml.kernel.org/r/a26121b294fdf76e369cb7a74351d1c03a908930.1612546384.git.andreyknvl@google.com Co-developed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Signed-off-by: Andrey Konovalov <andreyknvl@google.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Alexander Potapenko <glider@google.com> Cc: Andrey Ryabinin <aryabinin@virtuozzo.com> Cc: Branislav Rankov <Branislav.Rankov@arm.com> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: Evgenii Stepanov <eugenis@google.com> Cc: Kevin Brodsky <kevin.brodsky@arm.com> Cc: Marco Elver <elver@google.com> Cc: Peter Collingbourne <pcc@google.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
130 lines
3.2 KiB
C
130 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_CACHE_H
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#define __ASM_CACHE_H
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#include <asm/cputype.h>
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#define CTR_L1IP_SHIFT 14
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#define CTR_L1IP_MASK 3
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#define CTR_DMINLINE_SHIFT 16
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#define CTR_IMINLINE_SHIFT 0
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#define CTR_IMINLINE_MASK 0xf
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#define CTR_ERG_SHIFT 20
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#define CTR_CWG_SHIFT 24
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#define CTR_CWG_MASK 15
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#define CTR_IDC_SHIFT 28
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#define CTR_DIC_SHIFT 29
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#define CTR_CACHE_MINLINE_MASK \
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(0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
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#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
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#define ICACHE_POLICY_VPIPT 0
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#define ICACHE_POLICY_RESERVED 1
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#define ICACHE_POLICY_VIPT 2
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#define ICACHE_POLICY_PIPT 3
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#define L1_CACHE_SHIFT (6)
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define CLIDR_LOUU_SHIFT 27
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#define CLIDR_LOC_SHIFT 24
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#define CLIDR_LOUIS_SHIFT 21
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#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
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#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
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#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
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/*
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* Memory returned by kmalloc() may be used for DMA, so we must make
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* sure that all such allocations are cache aligned. Otherwise,
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* unrelated code may cause parts of the buffer to be read into the
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* cache before the transfer is done, causing old data to be seen by
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* the CPU.
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*/
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#define ARCH_DMA_MINALIGN (128)
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#ifdef CONFIG_KASAN_SW_TAGS
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#define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
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#elif defined(CONFIG_KASAN_HW_TAGS)
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#define ARCH_SLAB_MINALIGN MTE_GRANULE_SIZE
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#endif
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#define ICACHEF_ALIASING 0
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#define ICACHEF_VPIPT 1
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extern unsigned long __icache_flags;
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/*
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* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
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* permitted in the I-cache.
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*/
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static inline int icache_is_aliasing(void)
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{
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return test_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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static __always_inline int icache_is_vpipt(void)
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{
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return test_bit(ICACHEF_VPIPT, &__icache_flags);
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}
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static inline u32 cache_type_cwg(void)
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{
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return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
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}
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#define __read_mostly __section(".data..read_mostly")
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static inline int cache_line_size_of_cpu(void)
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{
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u32 cwg = cache_type_cwg();
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return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
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}
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int cache_line_size(void);
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/*
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* Read the effective value of CTR_EL0.
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*
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* According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
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* section D10.2.33 "CTR_EL0, Cache Type Register" :
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*
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* CTR_EL0.IDC reports the data cache clean requirements for
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* instruction to data coherence.
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*
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* 0 - dcache clean to PoU is required unless :
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* (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
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* 1 - dcache clean to PoU is not required for i-to-d coherence.
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*
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* This routine provides the CTR_EL0 with the IDC field updated to the
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* effective state.
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*/
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static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
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{
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u32 ctr = read_cpuid_cachetype();
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if (!(ctr & BIT(CTR_IDC_SHIFT))) {
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u64 clidr = read_sysreg(clidr_el1);
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if (CLIDR_LOC(clidr) == 0 ||
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(CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
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ctr |= BIT(CTR_IDC_SHIFT);
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}
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return ctr;
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}
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#endif /* __ASSEMBLY__ */
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#endif
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