forked from Minki/linux
13cde09003
o Fix some bugs of fsl_sai_set_dai_fmt_tr(). o Add SND_SOC_DAIFMT_LEFT_J support. o Add SND_SOC_DAIFMT_CBS_CFM support. o Add SND_SOC_DAIFMT_CBM_CFS support. o And SND_SOC_DAIFMT_RIGHT_J need to be done in the future. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
513 lines
12 KiB
C
513 lines
12 KiB
C
/*
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* Freescale ALSA SoC Digital Audio Interface (SAI) driver.
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*
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* Copyright 2012-2013 Freescale Semiconductor, Inc.
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*
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* This program is free software, you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 2 of the License, or(at your
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* option) any later version.
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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#include "fsl_sai.h"
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static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int fsl_dir)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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u32 val_cr2, reg_cr2;
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if (fsl_dir == FSL_FMT_TRANSMITTER)
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reg_cr2 = FSL_SAI_TCR2;
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else
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reg_cr2 = FSL_SAI_RCR2;
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regmap_read(sai->regmap, reg_cr2, &val_cr2);
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val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
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switch (clk_id) {
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case FSL_SAI_CLK_BUS:
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val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
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break;
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case FSL_SAI_CLK_MAST1:
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val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
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break;
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case FSL_SAI_CLK_MAST2:
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val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
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break;
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case FSL_SAI_CLK_MAST3:
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val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
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break;
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default:
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return -EINVAL;
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}
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regmap_write(sai->regmap, reg_cr2, val_cr2);
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return 0;
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}
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static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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int ret;
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if (dir == SND_SOC_CLOCK_IN)
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return 0;
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ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
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FSL_FMT_TRANSMITTER);
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if (ret) {
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dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
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return ret;
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}
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ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
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FSL_FMT_RECEIVER);
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if (ret)
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dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
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return ret;
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}
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static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
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unsigned int fmt, int fsl_dir)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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u32 val_cr2, val_cr4, reg_cr2, reg_cr4;
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if (fsl_dir == FSL_FMT_TRANSMITTER) {
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reg_cr2 = FSL_SAI_TCR2;
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reg_cr4 = FSL_SAI_TCR4;
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} else {
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reg_cr2 = FSL_SAI_RCR2;
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reg_cr4 = FSL_SAI_RCR4;
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}
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regmap_read(sai->regmap, reg_cr2, &val_cr2);
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regmap_read(sai->regmap, reg_cr4, &val_cr4);
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if (sai->big_endian_data)
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val_cr4 &= ~FSL_SAI_CR4_MF;
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else
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val_cr4 |= FSL_SAI_CR4_MF;
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/* DAI mode */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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/* Data on rising edge of bclk, frame low, 1clk before data */
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val_cr2 &= ~FSL_SAI_CR2_BCP;
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val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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/* Data on rising edge of bclk, frame high, 0clk before data */
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val_cr2 &= ~FSL_SAI_CR2_BCP;
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val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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/* To be done */
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default:
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return -EINVAL;
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}
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/* DAI clock inversion */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_IB_IF:
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/* Invert both clocks */
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val_cr2 ^= FSL_SAI_CR2_BCP;
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val_cr4 ^= FSL_SAI_CR4_FSP;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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/* Invert bit clock */
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val_cr2 ^= FSL_SAI_CR2_BCP;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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/* Invert frame clock */
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val_cr4 ^= FSL_SAI_CR4_FSP;
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break;
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case SND_SOC_DAIFMT_NB_NF:
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/* Nothing to do for both normal cases */
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break;
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default:
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return -EINVAL;
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}
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/* DAI clock master masks */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
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val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
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val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
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break;
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case SND_SOC_DAIFMT_CBS_CFM:
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val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
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val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
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val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
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break;
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default:
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return -EINVAL;
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}
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regmap_write(sai->regmap, reg_cr2, val_cr2);
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regmap_write(sai->regmap, reg_cr4, val_cr4);
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return 0;
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}
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static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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int ret;
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ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
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if (ret) {
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dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
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return ret;
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}
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ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
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if (ret)
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dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
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return ret;
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}
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static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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u32 val_cr4, val_cr5, val_mr, reg_cr4, reg_cr5, reg_mr;
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unsigned int channels = params_channels(params);
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u32 word_width = snd_pcm_format_width(params_format(params));
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_cr4 = FSL_SAI_TCR4;
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reg_cr5 = FSL_SAI_TCR5;
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reg_mr = FSL_SAI_TMR;
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} else {
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reg_cr4 = FSL_SAI_RCR4;
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reg_cr5 = FSL_SAI_RCR5;
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reg_mr = FSL_SAI_RMR;
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}
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regmap_read(sai->regmap, reg_cr4, &val_cr4);
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regmap_read(sai->regmap, reg_cr4, &val_cr5);
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val_cr4 &= ~FSL_SAI_CR4_SYWD_MASK;
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val_cr4 &= ~FSL_SAI_CR4_FRSZ_MASK;
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val_cr5 &= ~FSL_SAI_CR5_WNW_MASK;
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val_cr5 &= ~FSL_SAI_CR5_W0W_MASK;
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val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;
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val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
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val_cr5 |= FSL_SAI_CR5_WNW(word_width);
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val_cr5 |= FSL_SAI_CR5_W0W(word_width);
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val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;
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if (sai->big_endian_data)
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val_cr5 |= FSL_SAI_CR5_FBT(0);
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else
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val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
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val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
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val_mr = ~0UL - ((1 << channels) - 1);
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regmap_write(sai->regmap, reg_cr4, val_cr4);
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regmap_write(sai->regmap, reg_cr5, val_cr5);
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regmap_write(sai->regmap, reg_mr, val_mr);
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return 0;
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}
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static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *cpu_dai)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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u32 tcsr, rcsr;
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regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
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~FSL_SAI_CR2_SYNC);
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regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
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FSL_SAI_CR2_SYNC);
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regmap_read(sai->regmap, FSL_SAI_TCSR, &tcsr);
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regmap_read(sai->regmap, FSL_SAI_RCSR, &rcsr);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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tcsr |= FSL_SAI_CSR_FRDE;
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rcsr &= ~FSL_SAI_CSR_FRDE;
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} else {
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rcsr |= FSL_SAI_CSR_FRDE;
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tcsr &= ~FSL_SAI_CSR_FRDE;
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}
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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tcsr |= FSL_SAI_CSR_TERE;
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rcsr |= FSL_SAI_CSR_TERE;
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regmap_write(sai->regmap, FSL_SAI_RCSR, rcsr);
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regmap_write(sai->regmap, FSL_SAI_TCSR, tcsr);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (!(cpu_dai->playback_active || cpu_dai->capture_active)) {
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tcsr &= ~FSL_SAI_CSR_TERE;
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rcsr &= ~FSL_SAI_CSR_TERE;
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}
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regmap_write(sai->regmap, FSL_SAI_TCSR, tcsr);
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regmap_write(sai->regmap, FSL_SAI_RCSR, rcsr);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int fsl_sai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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u32 reg;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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reg = FSL_SAI_TCR3;
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else
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reg = FSL_SAI_RCR3;
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regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
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FSL_SAI_CR3_TRCE);
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return 0;
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}
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static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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u32 reg;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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reg = FSL_SAI_TCR3;
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else
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reg = FSL_SAI_RCR3;
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regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
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~FSL_SAI_CR3_TRCE);
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}
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static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
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.set_sysclk = fsl_sai_set_dai_sysclk,
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.set_fmt = fsl_sai_set_dai_fmt,
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.hw_params = fsl_sai_hw_params,
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.trigger = fsl_sai_trigger,
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.startup = fsl_sai_startup,
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.shutdown = fsl_sai_shutdown,
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};
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static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
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{
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struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
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regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, 0x0);
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, 0x0);
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regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
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FSL_SAI_MAXBURST_TX * 2);
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regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
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FSL_SAI_MAXBURST_RX - 1);
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snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
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&sai->dma_params_rx);
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snd_soc_dai_set_drvdata(cpu_dai, sai);
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return 0;
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}
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static struct snd_soc_dai_driver fsl_sai_dai = {
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.probe = fsl_sai_dai_probe,
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.playback = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = FSL_SAI_FORMATS,
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},
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.capture = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = FSL_SAI_FORMATS,
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},
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.ops = &fsl_sai_pcm_dai_ops,
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};
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static const struct snd_soc_component_driver fsl_component = {
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.name = "fsl-sai",
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};
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static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case FSL_SAI_TCSR:
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case FSL_SAI_TCR1:
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case FSL_SAI_TCR2:
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case FSL_SAI_TCR3:
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case FSL_SAI_TCR4:
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case FSL_SAI_TCR5:
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case FSL_SAI_TFR:
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case FSL_SAI_TMR:
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case FSL_SAI_RCSR:
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case FSL_SAI_RCR1:
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case FSL_SAI_RCR2:
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case FSL_SAI_RCR3:
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case FSL_SAI_RCR4:
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case FSL_SAI_RCR5:
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case FSL_SAI_RDR:
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case FSL_SAI_RFR:
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case FSL_SAI_RMR:
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return true;
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default:
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return false;
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}
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}
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static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case FSL_SAI_TFR:
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case FSL_SAI_RFR:
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case FSL_SAI_TDR:
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case FSL_SAI_RDR:
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return true;
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default:
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return false;
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}
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}
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static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case FSL_SAI_TCSR:
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case FSL_SAI_TCR1:
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case FSL_SAI_TCR2:
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case FSL_SAI_TCR3:
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case FSL_SAI_TCR4:
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case FSL_SAI_TCR5:
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case FSL_SAI_TDR:
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case FSL_SAI_TMR:
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case FSL_SAI_RCSR:
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case FSL_SAI_RCR1:
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case FSL_SAI_RCR2:
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case FSL_SAI_RCR3:
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case FSL_SAI_RCR4:
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case FSL_SAI_RCR5:
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case FSL_SAI_RMR:
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return true;
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default:
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return false;
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}
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}
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static struct regmap_config fsl_sai_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = FSL_SAI_RMR,
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.readable_reg = fsl_sai_readable_reg,
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.volatile_reg = fsl_sai_volatile_reg,
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.writeable_reg = fsl_sai_writeable_reg,
|
|
};
|
|
|
|
static int fsl_sai_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct fsl_sai *sai;
|
|
struct resource *res;
|
|
void __iomem *base;
|
|
int ret;
|
|
|
|
sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
|
|
if (!sai)
|
|
return -ENOMEM;
|
|
|
|
sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
|
|
if (sai->big_endian_regs)
|
|
fsl_sai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
|
|
|
|
sai->big_endian_data = of_property_read_bool(np, "big-endian-data");
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
|
|
"sai", base, &fsl_sai_regmap_config);
|
|
if (IS_ERR(sai->regmap)) {
|
|
dev_err(&pdev->dev, "regmap init failed\n");
|
|
return PTR_ERR(sai->regmap);
|
|
}
|
|
|
|
sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
|
|
sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
|
|
sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
|
|
sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
|
|
|
|
platform_set_drvdata(pdev, sai);
|
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
|
|
&fsl_sai_dai, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
|
|
SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
|
|
}
|
|
|
|
static const struct of_device_id fsl_sai_ids[] = {
|
|
{ .compatible = "fsl,vf610-sai", },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static struct platform_driver fsl_sai_driver = {
|
|
.probe = fsl_sai_probe,
|
|
.driver = {
|
|
.name = "fsl-sai",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = fsl_sai_ids,
|
|
},
|
|
};
|
|
module_platform_driver(fsl_sai_driver);
|
|
|
|
MODULE_DESCRIPTION("Freescale Soc SAI Interface");
|
|
MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
|
|
MODULE_ALIAS("platform:fsl-sai");
|
|
MODULE_LICENSE("GPL");
|