forked from Minki/linux
9bf41be673
Currently, we're using the combo (PCI bus + devfn) in the PCI config accessors and PCI config accessors in EEH depends on them. However, it's not safe to refer the PCI bus which might have been removed during hotplug. So we're using device node in the PCI config accessors and the corresponding backends just reuse them. The patch also fix one potential risk: We possiblly have frozen PE during the early PCI probe time, but we haven't setup the PE mapping yet. So the errors should be counted to PE#0. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
199 lines
4.9 KiB
C
199 lines
4.9 KiB
C
#ifndef __POWERNV_PCI_H
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#define __POWERNV_PCI_H
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struct pci_dn;
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enum pnv_phb_type {
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PNV_PHB_P5IOC2 = 0,
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PNV_PHB_IODA1 = 1,
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PNV_PHB_IODA2 = 2,
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};
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/* Precise PHB model for error management */
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enum pnv_phb_model {
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PNV_PHB_MODEL_UNKNOWN,
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PNV_PHB_MODEL_P5IOC2,
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PNV_PHB_MODEL_P7IOC,
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PNV_PHB_MODEL_PHB3,
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};
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#define PNV_PCI_DIAG_BUF_SIZE 4096
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#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
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#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
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#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
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/* Data associated with a PE, including IOMMU tracking etc.. */
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struct pnv_phb;
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struct pnv_ioda_pe {
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unsigned long flags;
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struct pnv_phb *phb;
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/* A PE can be associated with a single device or an
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* entire bus (& children). In the former case, pdev
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* is populated, in the later case, pbus is.
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*/
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struct pci_dev *pdev;
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struct pci_bus *pbus;
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/* Effective RID (device RID for a device PE and base bus
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* RID with devfn 0 for a bus PE)
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*/
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unsigned int rid;
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/* PE number */
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unsigned int pe_number;
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/* "Weight" assigned to the PE for the sake of DMA resource
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* allocations
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*/
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unsigned int dma_weight;
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/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
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int tce32_seg;
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int tce32_segcount;
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struct iommu_table tce32_table;
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/* XXX TODO: Add support for additional 64-bit iommus */
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/* MSIs. MVE index is identical for for 32 and 64 bit MSI
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* and -1 if not supported. (It's actually identical to the
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* PE number)
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*/
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int mve_number;
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/* Link in list of PE#s */
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struct list_head dma_link;
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struct list_head list;
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};
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/* IOC dependent EEH operations */
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#ifdef CONFIG_EEH
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struct pnv_eeh_ops {
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int (*post_init)(struct pci_controller *hose);
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int (*set_option)(struct eeh_pe *pe, int option);
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int (*get_state)(struct eeh_pe *pe);
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int (*reset)(struct eeh_pe *pe, int option);
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int (*get_log)(struct eeh_pe *pe, int severity,
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char *drv_log, unsigned long len);
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int (*configure_bridge)(struct eeh_pe *pe);
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int (*next_error)(struct eeh_pe **pe);
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};
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#define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */
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#define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */
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#endif /* CONFIG_EEH */
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struct pnv_phb {
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struct pci_controller *hose;
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enum pnv_phb_type type;
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enum pnv_phb_model model;
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u64 hub_id;
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u64 opal_id;
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void __iomem *regs;
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int initialized;
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spinlock_t lock;
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#ifdef CONFIG_EEH
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struct pnv_eeh_ops *eeh_ops;
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int eeh_state;
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#endif
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#ifdef CONFIG_DEBUG_FS
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struct dentry *dbgfs;
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#endif
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#ifdef CONFIG_PCI_MSI
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unsigned int msi_base;
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unsigned int msi32_support;
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struct msi_bitmap msi_bmp;
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#endif
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int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int hwirq, unsigned int virq,
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unsigned int is_64, struct msi_msg *msg);
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void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
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void (*fixup_phb)(struct pci_controller *hose);
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u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
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void (*shutdown)(struct pnv_phb *phb);
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union {
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struct {
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struct iommu_table iommu_table;
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} p5ioc2;
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struct {
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/* Global bridge info */
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unsigned int total_pe;
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unsigned int m32_size;
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unsigned int m32_segsize;
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unsigned int m32_pci_base;
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unsigned int io_size;
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unsigned int io_segsize;
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unsigned int io_pci_base;
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/* PE allocation bitmap */
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unsigned long *pe_alloc;
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/* M32 & IO segment maps */
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unsigned int *m32_segmap;
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unsigned int *io_segmap;
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struct pnv_ioda_pe *pe_array;
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/* IRQ chip */
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int irq_chip_init;
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struct irq_chip irq_chip;
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/* Sorted list of used PE's based
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* on the sequence of creation
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*/
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struct list_head pe_list;
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/* Reverse map of PEs, will have to extend if
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* we are to support more than 256 PEs, indexed
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* bus { bus, devfn }
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*/
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unsigned char pe_rmap[0x10000];
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/* 32-bit TCE tables allocation */
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unsigned long tce32_count;
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/* Total "weight" for the sake of DMA resources
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* allocation
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*/
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unsigned int dma_weight;
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unsigned int dma_pe_count;
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/* Sorted list of used PE's, sorted at
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* boot for resource allocation purposes
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*/
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struct list_head pe_dma_list;
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} ioda;
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};
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/* PHB status structure */
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union {
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unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
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struct OpalIoP7IOCPhbErrorData p7ioc;
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} diag;
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};
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extern struct pci_ops pnv_pci_ops;
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#ifdef CONFIG_EEH
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extern struct pnv_eeh_ops ioda_eeh_ops;
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#endif
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int pnv_pci_cfg_read(struct device_node *dn,
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int where, int size, u32 *val);
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int pnv_pci_cfg_write(struct device_node *dn,
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int where, int size, u32 val);
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extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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void *tce_mem, u64 tce_size,
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u64 dma_offset);
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extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
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extern void pnv_pci_init_ioda_hub(struct device_node *np);
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extern void pnv_pci_init_ioda2_phb(struct device_node *np);
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extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
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u64 *startp, u64 *endp);
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#endif /* __POWERNV_PCI_H */
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