Eric Yang 133e8e1b35 drm/amd/display: Change how we disable pipe split ... Before this change, pipe split was disabled by bumping up dpp clock bounding box for DPM level 0 and 1, this allows validation to pass without splitting at a lower DPM level. This change reverts this and instead lowers display clock at DPM level 0, this forces configurations that need pipe split at DPM level 0 to go to DPM level 1, where they can be driven without split. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-09-26 18:08:40 -04:00
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amdgpu_dm	drm/amd/display: Remove acrtc->stream	2017-09-26 18:08:37 -04:00
dc	drm/amd/display: Change how we disable pipe split	2017-09-26 18:08:40 -04:00
include	drm/amd/display: Add extra mode and clock info to DTN logs	2017-09-26 18:08:24 -04:00
modules	drm/amd/display: Re-enable Vsync Interrupts for Gradual Refresh Ramp	2017-09-26 18:08:27 -04:00
Kconfig	drm/amd/display: Limit DCN to x86 arch	2017-09-26 18:07:32 -04:00
Makefile