forked from Minki/linux
955c9863bb
Convert the processor platform device setup functions from __initcall() and sometimes device_initcall() to arch_initcall(). This makes sure that the platform devices are registered a bit earlier so the devices are available when drivers register using initcall levels earlier than device_initcall(). A good example is platform devices needed by i2c-sh_mobile.c which registers a bit earlier using subsys_initcall(). Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
383 lines
9.5 KiB
C
383 lines
9.5 KiB
C
/*
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* SH7201 setup
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*
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* Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
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* Copyright (C) 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <linux/io.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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ADC_ADI,
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MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
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MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
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RTC, WDT,
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IIC30, IIC31, IIC32,
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DMAC0_DMINT0, DMAC1_DMINT1,
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DMAC2_DMINT2, DMAC3_DMINT3,
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SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
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DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
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DMAC7_DMINT7,
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RCAN0, RCAN1,
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SSI0_SSII, SSI1_SSII,
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TMR0, TMR1,
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/* interrupt groups */
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PINT,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(ADC_ADI, 92),
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INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
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INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
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INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
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INTC_IRQ(MTU20_VEF, 114),
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INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
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INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
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INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
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INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
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INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
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INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
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INTC_IRQ(MTU2_TCI3V, 136),
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INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
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INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
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INTC_IRQ(MTU2_TCI4V, 144),
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INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
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INTC_IRQ(MTU25_UVW, 150),
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INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
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INTC_IRQ(RTC, 154),
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INTC_IRQ(WDT, 156),
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INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
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INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
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INTC_IRQ(IIC30, 161),
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INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
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INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
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INTC_IRQ(IIC31, 168),
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INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
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INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
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INTC_IRQ(IIC32, 174),
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INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
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INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
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INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
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INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
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INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
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INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
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INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
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INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
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INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
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INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
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INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
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INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
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INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
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INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
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INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
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INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
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INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
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INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
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INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
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INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
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INTC_IRQ(DMAC7_DMINT7, 219),
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INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
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INTC_IRQ(RCAN0, 230),
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INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
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INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
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INTC_IRQ(RCAN1, 236),
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INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
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INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
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INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
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INTC_IRQ(TMR0, 248),
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INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
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INTC_IRQ(TMR1, 254),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
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{ 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
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{ 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } },
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{ 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
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{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
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{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
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{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
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{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
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{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
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{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
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{ 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
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{ 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfffe9408, 0, 16, /* PINTER */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
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mask_registers, prio_registers, NULL);
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xfffe8000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 180, 180, 180, 180 }
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}, {
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.mapbase = 0xfffe8800,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 184, 184, 184, 184 }
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}, {
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.mapbase = 0xfffe9000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 188, 188, 188, 188 }
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}, {
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.mapbase = 0xfffe9800,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 192, 192, 192, 192 }
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}, {
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.mapbase = 0xfffea000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 196, 196, 196, 196 }
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}, {
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.mapbase = 0xfffea800,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 200, 200, 200, 200 }
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}, {
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.mapbase = 0xfffeb000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 204, 204, 204, 204 }
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}, {
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.mapbase = 0xfffeb800,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 208, 208, 208, 208 }
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xffff0800,
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.end = 0xffff2000 + 0x58 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Shared Period/Carry/Alarm IRQ */
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.start = 152,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct sh_timer_config mtu2_0_platform_data = {
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.name = "MTU2_0",
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.channel_offset = -0x80,
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.timer_bit = 0,
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.clk = "peripheral_clk",
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.clockevent_rating = 200,
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};
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static struct resource mtu2_0_resources[] = {
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[0] = {
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.name = "MTU2_0",
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.start = 0xfffe4300,
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.end = 0xfffe4326,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 108,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mtu2_0_device = {
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.name = "sh_mtu2",
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.id = 0,
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.dev = {
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.platform_data = &mtu2_0_platform_data,
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},
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.resource = mtu2_0_resources,
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.num_resources = ARRAY_SIZE(mtu2_0_resources),
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};
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static struct sh_timer_config mtu2_1_platform_data = {
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.name = "MTU2_1",
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.channel_offset = -0x100,
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.timer_bit = 1,
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.clk = "peripheral_clk",
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.clockevent_rating = 200,
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};
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static struct resource mtu2_1_resources[] = {
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[0] = {
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.name = "MTU2_1",
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.start = 0xfffe4380,
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.end = 0xfffe4390,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 116,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mtu2_1_device = {
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.name = "sh_mtu2",
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.id = 1,
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.dev = {
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.platform_data = &mtu2_1_platform_data,
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},
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.resource = mtu2_1_resources,
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.num_resources = ARRAY_SIZE(mtu2_1_resources),
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};
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static struct sh_timer_config mtu2_2_platform_data = {
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.name = "MTU2_2",
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.channel_offset = 0x80,
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.timer_bit = 2,
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.clk = "peripheral_clk",
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.clockevent_rating = 200,
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};
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static struct resource mtu2_2_resources[] = {
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[0] = {
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.name = "MTU2_2",
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.start = 0xfffe4000,
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.end = 0xfffe400a,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 124,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mtu2_2_device = {
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.name = "sh_mtu2",
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.id = 2,
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.dev = {
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.platform_data = &mtu2_2_platform_data,
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},
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.resource = mtu2_2_resources,
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.num_resources = ARRAY_SIZE(mtu2_2_resources),
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};
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static struct platform_device *sh7201_devices[] __initdata = {
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&sci_device,
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&rtc_device,
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&mtu2_0_device,
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&mtu2_1_device,
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&mtu2_2_device,
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};
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static int __init sh7201_devices_setup(void)
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{
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return platform_add_devices(sh7201_devices,
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ARRAY_SIZE(sh7201_devices));
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}
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arch_initcall(sh7201_devices_setup);
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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}
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static struct platform_device *sh7201_early_devices[] __initdata = {
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&mtu2_0_device,
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&mtu2_1_device,
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&mtu2_2_device,
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};
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#define STBCR3 0xfffe0408
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void __init plat_early_device_setup(void)
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{
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/* enable MTU2 clock */
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__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
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early_platform_add_devices(sh7201_early_devices,
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ARRAY_SIZE(sh7201_early_devices));
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}
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