forked from Minki/linux
5e73761786
The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same silicon, and all share the same clocks. However, they're not packaged in the same way, and therefore not all the controllers are actually available on all these SoCs. Introduce a clock controller driver for all these SoCs with different compatibles to take that into account. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
104 lines
2.5 KiB
C
104 lines
2.5 KiB
C
/*
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* Copyright 2016 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_SUN5I_H_
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#define _DT_BINDINGS_CLK_SUN5I_H_
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#define CLK_HOSC 1
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#define CLK_CPU 17
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#define CLK_AHB_OTG 23
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#define CLK_AHB_EHCI 24
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#define CLK_AHB_OHCI 25
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#define CLK_AHB_SS 26
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#define CLK_AHB_DMA 27
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#define CLK_AHB_BIST 28
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#define CLK_AHB_MMC0 29
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#define CLK_AHB_MMC1 30
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#define CLK_AHB_MMC2 31
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#define CLK_AHB_NAND 32
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#define CLK_AHB_SDRAM 33
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#define CLK_AHB_EMAC 34
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#define CLK_AHB_TS 35
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#define CLK_AHB_SPI0 36
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#define CLK_AHB_SPI1 37
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#define CLK_AHB_SPI2 38
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#define CLK_AHB_GPS 39
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#define CLK_AHB_HSTIMER 40
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#define CLK_AHB_VE 41
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#define CLK_AHB_TVE 42
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#define CLK_AHB_LCD 43
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#define CLK_AHB_CSI 44
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#define CLK_AHB_HDMI 45
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#define CLK_AHB_DE_BE 46
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#define CLK_AHB_DE_FE 47
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#define CLK_AHB_IEP 48
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#define CLK_AHB_GPU 49
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#define CLK_APB0_CODEC 50
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#define CLK_APB0_SPDIF 51
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#define CLK_APB0_I2S 52
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#define CLK_APB0_PIO 53
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#define CLK_APB0_IR 54
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#define CLK_APB0_KEYPAD 55
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#define CLK_APB1_I2C0 56
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#define CLK_APB1_I2C1 57
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#define CLK_APB1_I2C2 58
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#define CLK_APB1_UART0 59
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#define CLK_APB1_UART1 60
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#define CLK_APB1_UART2 61
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#define CLK_APB1_UART3 62
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#define CLK_NAND 63
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#define CLK_MMC0 64
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#define CLK_MMC1 65
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#define CLK_MMC2 66
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#define CLK_TS 67
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#define CLK_SS 68
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#define CLK_SPI0 69
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#define CLK_SPI1 70
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#define CLK_SPI2 71
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#define CLK_IR 72
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#define CLK_I2S 73
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#define CLK_SPDIF 74
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#define CLK_KEYPAD 75
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#define CLK_USB_OHCI 76
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#define CLK_USB_PHY0 77
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#define CLK_USB_PHY1 78
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#define CLK_GPS 79
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#define CLK_DRAM_VE 80
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#define CLK_DRAM_CSI 81
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#define CLK_DRAM_TS 82
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#define CLK_DRAM_TVE 83
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#define CLK_DRAM_DE_FE 84
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#define CLK_DRAM_DE_BE 85
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#define CLK_DRAM_ACE 86
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#define CLK_DRAM_IEP 87
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#define CLK_DE_BE 88
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#define CLK_DE_FE 89
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#define CLK_TCON_CH0 90
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#define CLK_TCON_CH1 92
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#define CLK_CSI 93
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#define CLK_VE 94
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#define CLK_CODEC 95
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#define CLK_AVS 96
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#define CLK_HDMI 97
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#define CLK_GPU 98
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#define CLK_IEP 100
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#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
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